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A.A. Gaffar
Researcher at Imperial College London
Publications - 12
Citations - 698
A.A. Gaffar is an academic researcher from Imperial College London. The author has contributed to research in topics: Field-programmable gate array & Floating point. The author has an hindex of 11, co-authored 12 publications receiving 678 citations.
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Journal ArticleDOI
Accuracy-Guaranteed Bit-Width Optimization
TL;DR: An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented and is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA.
Proceedings ArticleDOI
Unifying bit-width optimisation for fixed-point and floating-point designs
TL;DR: A method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs and is implemented in the BitSize tool targeting reconfigurable architectures, which takes user-defined constraints to direct the optimisation procedure.
Proceedings ArticleDOI
Floating-point bitwidth analysis via automatic differentiation
TL;DR: This work presents a novel approach to bitwidth- or precision-analysis for floating-point designs, which involves analysing the dataflow graph representation of a design to see how sensitive the output of a node is to changes in the outputs of other nodes: higher sensitivity requires higher precision and hence more output bits.
Journal ArticleDOI
Optimizing hardware function evaluation
TL;DR: Over 2,000 placed-and-routed FPGA designs are implemented, resulting in over 100 million application-specific integrated circuit (ASIC) equivalent gates, and optimal function evaluation results for range and precision combinations between 8 and 48 bits are provided.
Proceedings ArticleDOI
MiniBit: bit-width optimization via affine arithmetic
TL;DR: This work describes methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area and employs a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits.