A. Alaerts

Bio: A. Alaerts is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Wafer & Radiation hardening. The author has an hindex of 3, co-authored 5 publications receiving 48 citations.

Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers

Abstract: A new approach to monolithic pixel detectors, based on silicon on insulator (SOI) wafers with high resistivity substrate, is being pursued by the CERN RD19 collaboration. The fabrication methods and the results of the electrical evaluation of the SOI-MOSFET devices and of the detector structures fabricated in the bulk are reported. The leakage current of the high-resistivity PIN-diodes is kept of the order of 5 to 10 nA/cm/sup 2/. The SOI preparation processes employed-SIMOX (separation by implantation of oxygen) and ZMR (zone melting recrystallization)-produce working electronic circuits, and appear to be compatible with the fabrication of detectors of suitable quality. >

Ionizing radiation hardening of a CCD technology

Abstract: A three-level polysilicon, buried channel charge coupled device (CCD) technology has been tested for Co/sup 60/ ionizing radiation damage up to a total dose of 90 krad(Si). For this purpose CCD image sensors have been irradiated together with their associated test structures. These include different types of MOSFETs, natural transistors, buried channel transistors, field transistors, and diodes. The devices have been fully characterized during irradiation and afterwards, as a function of time. The standard technology has been assessed, leading to the implementation of process and design modifications. The modified technology has been further tested according to the same procedure and significant improvement in the sensors' behavior under irradiation and during annealing has been observed. The radiation hardness of the CCDs has been correlated with the results of the test structures, allowing a better understanding of the degradation phenomena and of the countermeasures needed for a radiation-hardened technology. >

Integration of CMOS-electronics in an SOI layer on high-resistivity silicon substrates

Abstract: The monolithic integration of electronics and high-resistivity silicon detectors is reported. The approach is based on CMOS circuit integration in the top layer of high-resistivity SOI (silicon-on-insulator) wafers. In a preliminary feasibility study, high-resistivity wafers were subjected to SOI layer fabrication methods and evaluated with a simple diode process for two main characteristics: diode leakage and possible dopant concentration increase. In the second phase of the project, a full SOI-on-H Omega process was executed. MOSFET behavior was then evaluated. >

Characterization of the Ionizing Radiation Sensitivity of a CCD Technology

Abstract: The radiation hardness of a Charge Coupled Device (CCD) technology was characterized with respect to ionizing irradiation. Image sensors and their associated drop-in structures were exposed to ?-rays up to a total dose of 90 krad(Si). In this paper results on CCD's and test structures are presented and the degradation phenomena are discussed.

Radiation effects and hardening of MOS technology: devices and circuits

Abstract: Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

The low-frequency noise behaviour of silicon-on-insulator technologies

Abstract: In this overview, the low-frequency noise behaviour of devices fabricated in silicon-on-insulator technologies is described. The different potential noise sources are analysed and illustrated by experimental results, mainly obtained on MOSFETs. Some SOI-specific noise behaviour is highlighted, as for instance the kink-related excess low-frequency noise overshoot. It is shown furthermore that SOI MOSFETs suffer from so-called random telegraph signals, which can originate from the front- or the back-gate dielectric, or from defects located in the thin Si active layer. The impact of the substrate type (SIMOX, bonded, ZMR,…) is discussed. At the same time, it is shown that the used technology and device structure can have a pronounced effect on the LF noise performance. Finally, the response of SOI MOSFETs on ionizing radiation (γs, X-rays,…) is studied through the LF noise degradation, in view of radiation-hardened applications.

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

Abstract: Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design a ...

Semiconductor micropattern pixel detectors: a review of the beginnings

Abstract: The innovation in monolithic and hybrid semiconductor ‘micropattern’ or ‘reactive’ pixel detectors for tracking in particle physics was actually to fit logic and pulse processing electronics with μW power on a pixel area of less than 0.04 mm 2 , retaining the characteristics of a traditional nuclear amplifier chain. The ns timing precision in conjunction with local memory and logic operations allowed event selection at >10 MHz rates with unambiguous track reconstruction even at particle multiplicities >10 cm −2 . The noise in a channel was ∼100 e − rms and enabled binary operation with random noise ‘hits’ at a level 75 μm ×500 μm down to 34 μm ×125 μm have been used by different teams. In binary mode a tracking precision from 6 to 14 μm was obtained, and using analog interpolation one came close to 1 μm . Earlier work, still based on charge integrating imaging circuits, provided a starting point. Two systems each with more than 1 million sensor + readout channels have been built, for WA97-NA57 and for the Delphi very forward tracker. The use of 0.5 μm and 0.25 μm CMOS and enclosed geometry for the transistors in the pixel readout chips resulted in radiation hardness of ∼2 Mrad , respectively, >30 Mrad .

Electron and neutron radiation damage effects on a two-phase CCD

Abstract: Surface and bulk radiation damage effects on a two-phase charge-coupled device (CCD), operated in a multipinned phase (MPP) mode have been evaluated Two-phase CCD's are one of the candidates for application in the vertex detector of a future linear collider Flat-band voltage shifts, dark current, dark current spikes, and charge transfer efficiency (CTE) were studied on devices subjected to irradiation with fluences reaching 43/spl times/10/sup 12/ electrons/cm/sup 2/ and 89/spl times/10/sup 9/ neutrons/cm/sup 2/ An additional source of dark signal in electron irradiated devices was observed and explained by impact ionization by holes, released by tunneling from defect states near the Si-SiO/sub 2/ interface A model for the CTE in a two-phase CCD as a function of temperature, background charges, and clock timing is described Calculations based on the model are in good agreement with the experimentally determined values of CTE in electron and neutron irradiated CCD's