A. Amerasekera

Bio: A. Amerasekera is an academic researcher from Philips. The author has contributed to research in topics: Electrostatic discharge & Snapback. The author has an hindex of 2, co-authored 2 publications receiving 201 citations.

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

Abstract: A technique is presented to determine the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs, for use in the development of electrostatic discharge (ESD) protection circuits. Test structures from a fully salicided, LDD MOS process were characterized with a transmission line pulse generator to obtain the snapback voltages and the second-breakdown trigger currents (I/sub t2/) Good correlations are shown between I/sub t2/ and the human body model (HBM) ESD damage thresholds. It was seen that homogeneous current injection in the avalanching diffusions is imperative for good second breakdown behavior. A simplified thermal model, with second breakdown as the boundary condition for damage, was used in the extraction of the effective junction depth, depletion width, and transistor width under high-current conditions. Experimental data obtained for the power-to-failure as a function of the time-to-failure showed a good fit to the model. A possible extension of the technique for the use of DC characterization to monitor ESD behavior is presented. >

ESD failure modes: characteristics mechanisms, and process influences

Abstract: Electrostatic discharge (ESD) failure modes in advanced CMOS processes have been electrically and physically characterized, and an analysis has been made of the mechanisms of each of the main failure modes. The physical failure modes have been related to the electrical degradation and, therefore, the electrical signatures of the damage mechanisms have been obtained. The distribution of the electrical characteristics after ESD stress, for a given process or design variation, can then be used to identify freak failures and process defects. Investigations of the influence of processing steps such as silicides, lightly doped drains (LDDs), thin gate oxides, bird's-beak suppression, and barrier metallization on the electrical damage characteristics and the failure modes are presented and analyzed. >

ESD in silicon integrated circuits

Abstract: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

Nanoscale design to enable the revolution in renewable energy

Abstract: The creation of a sustainable energy generation, storage, and distribution infrastructure represents a global grand challenge that requires massive transnational investments in the research and development of energy technologies that will provide the amount of energy needed on a sufficient scale and timeframe with minimal impact on the environment and have limited economic and societal disruption during implementation. In this opinion paper, we focus on an important set of solar, thermal, and electrochemical energy conversion, storage, and conservation technologies specifically related to recent and prospective advances in nanoscale science and technology that offer high potential in addressing the energy challenge. We approach this task from a two-fold perspective: analyzing the fundamental physicochemical principles and engineering aspects of these energy technologies and identifying unique opportunities enabled by nanoscale design of materials, processes, and systems in order to improve performance and reduce costs. Our principal goal is to establish a roadmap for research and development activities in nanoscale science and technology that would significantly advance and accelerate the implementation of renewable energy technologies. In all cases we make specific recommendations for research needs in the near-term (2–5 years), mid-term (5–10 years) and long-term (>10 years), as well as projecting a timeline for maturation of each technological solution. We also identify a number of priority themes in basic energy science that cut across the entire spectrum of energy conversion, storage, and conservation technologies. We anticipate that the conclusions and recommendations herein will be of use not only to the technical community, but also to policy makers and the broader public, occasionally with an admitted emphasis on the US perspective.

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

TLP calibration, correlation, standards, and new techniques

Abstract: This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at transmission line pulse (TLP) data, beyond the I-V curves. Accurate TLP measurements and actual TLP/HBM device data are used to demonstrate dV/dt effects and HBM/TLP correlation and miscorrelation. Finally, a calibration method and standard TLP test method are presented for adaptation by the industry. This is necessary to provide correlation and repeatability of experimental data.

The impact of technology scaling on ESD robustness and protection circuit design

Abstract: The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness. >