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A. Amerasekera

Bio: A. Amerasekera is an academic researcher from Texas Instruments. The author has contributed to research in topics: Electrostatic discharge & Semiconductor device modeling. The author has an hindex of 15, co-authored 22 publications receiving 864 citations. Previous affiliations of A. Amerasekera include University of California, Berkeley.

Papers
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Proceedings ArticleDOI
01 Jan 1996
TL;DR: In this article, a circuit-level simulator for ESD and EOS is presented, which uses the three terminal currents obtained from a single high current I-V curve, and compared to experimental data for single devices as well as a practical output circuit.
Abstract: A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

146 citations

Proceedings ArticleDOI
26 Sep 2000
TL;DR: In this article, a floating guardring is used to pump the local substrate of the protection NMOS to achieve uniform npn protection in a multi-finger NMOS for advanced CMOS technologies with silicide.
Abstract: The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.

96 citations

Journal ArticleDOI
TL;DR: In this article, a model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects.
Abstract: Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 /spl mu/m CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects.

80 citations

Proceedings ArticleDOI
01 Dec 1996
TL;DR: In this article, the effect of interconnect scaling and low-k dielectric on the thermal characteristics of the interconnect structures has been characterized for the first time under DC and pulsed current conditions.
Abstract: The effect of interconnect scaling and low-k dielectric on the thermal characteristics of interconnect structures has been characterized for the first time under DC and pulsed current conditions It is shown that under DC conditions the thermal impedance of metal lines increases by about 10% when low-k dielectric is used as the gap fill The critical current density for the low-k structures under pulsed condition is shown to be about 10-30% lower than that of standard dielectric structures depending on metal and pulse widths

78 citations

Proceedings ArticleDOI
01 Jan 1996
TL;DR: In this article, a model for heating under ESD conditions is presented and it is shown that thermal breakdown occurs when the resistances increase by a factor of > 3.6 due to melting of metal lines.
Abstract: The high current and ESD effects on VLSI interconnect metallization have been characterized and a model for heating under ESD conditions is presented. It is shown that thermal breakdown occurs when the resistances increase by a factor of >3.6 due to melting of metal lines. After the metal is molten, the thermal stress is required to exceed the fracture strength of the oxide/nitride layers in order for the overlying dielectric to be cracked and an open circuit to take place. The critical failure current is strongly influenced by the metal thickness and thermal capacity. It is shown that for current pulses below the failure threshold, the metal will return to its original solid state with no change in DC resistance, but it will have a lower electromigration lifetime. This is a potential latent failure. The model is applied to derive relations between critical current, line width and pulse width for determining design guidelines for ESD and I/O buffer interconnects.

60 citations


Cited by
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Journal ArticleDOI
01 May 2001
TL;DR: This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.
Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

1,057 citations

Journal ArticleDOI
TL;DR: In this article, the authors present recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures, including silicon transistors, carbon nanostructures, and semiconductor nanowires.
Abstract: Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (∼10−8 W) to massive data centers (∼109 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces. Open image in new window

994 citations

Journal ArticleDOI
TL;DR: In this article, the authors present recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures, including silicon transistors, carbon nanostructures, and semiconductor nanowires.
Abstract: Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (~10^-8 W) to massive data centers (~10^9 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces.

838 citations

Journal ArticleDOI
TL;DR: In this article, the authors review recent advances in experimental methods for high spatial-resolution and high time-resolution thermometry and the application of these and related methods for measurements of thermal transport in low-dimensional structures.
Abstract: We review recent advances in experimental methods for high spatial-resolution and high time-resolution thermometry, and the application of these and related methods for measurements of thermal transport in low-dimensional structures. Scanning thermal microscopy (SThM) achieves lateral resolutions of 50 nm and a measurement bandwidth of 100 kHz: SThM has been used to characterize differences in energy dissipation in single-wall and multi-wall carbon nanotubes. Picosecond thermoreflectance enables ultrahigh time-resolution in thermal diffusion experiments and characterization of heat flow across interfaces between materials; the thermal conductance G of interfaces between dissimilar materials spans a relatively small range, 20

603 citations

Journal ArticleDOI
01 Mar 2001
TL;DR: This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands and one potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance.
Abstract: Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

572 citations