A. Arulmurugan

Bio: A. Arulmurugan is an academic researcher from Kongu Engineering College. The author has contributed to research in topics: Circuit reliability & Low-power electronics. The author has an hindex of 2, co-authored 2 publications receiving 208 citations.

Survey of low power testing of VLSI circuits

Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.

Survey of Low Power Testing of VLSI Circuits

Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques

XG Boost Algorithm based Hardware Trojan Detection in Hardware Circuits

Abstract: Hardware security is a protection that comes in the form of a physical device. A hardware security module provides security for sensitive data. Hardware trojan is an intentionally altered circuit of an Integrated Circuits chip. It may be during the chip formation or fabrication that is the chip is widened without the probable knowledge of the person who designed it. The Trojan leaks the information and malfunctions during crucial operations to getting around security precautions. They can also capture keystrokes or record the passwords entered by the users frequently. The trojans can be detected effectively by developing the machine learning models. Machine learning algorithms can achieve much higher accuracy while making predictions or classifying labelled data. XGBoost in machine learning algorithm is incredibly quick as it uses tree-based models and strives for best class accuracy. The feature set is trained using the XGBoost algorithm, which classifies the circuit into suspected Trojan circuits and regular circuits. The accuracy score achieved while making predictions using the Gradient Boosting algorithm is 99.43%.

Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes

Abstract: This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single-input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are evaluated. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.

Variation-aware speed binning of multi-core processors

Abstract: Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

Abstract: Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely “iFill”, to address the above issue, by analyzing the impact of X-bits on switching activities of the circuit nodes in the two different phases. In addition, different from prior X -filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.

Contribution au test et à la fiabilité des systèmes sur puce

Abstract: Ce document presente la synthese de mes travaux de recherche et d’enseignement effectues depuis septembre 1998, date a laquelle j’ai debute ma these de doctorat. Les travaux de recherche ont ete effectues au LIRMM (Laboratoire d’Informatique, de Robotique et de Microelectronique de Montpellier) au sein du departement de Microelectronique. Les activites d’enseignement ont ete menees a la Faculte des sciences (ex UFR) / departement EEA (Electronique, Electrotechnique et Automatique) de l’Universite Montpellier 2 au niveau Licence et Master.