scispace - formally typeset
Search or ask a question
Author

A. Carbine

Bio: A. Carbine is an academic researcher from Intel. The author has contributed to research in topics: Design for testing & Time to market. The author has an hindex of 1, co-authored 1 publications receiving 66 citations.

Papers
More filters
Journal ArticleDOI
A. Carbine1, D. Feltham
TL;DR: The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led this design team to a custom, low-area DFT approach and a manually written test methodology that targeted several fault models.
Abstract: The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led this design team to a custom, low-area DFT approach and a manually written test methodology that targeted several fault models. Their approach effectively balanced testability needs with other design constraints, while enabling excellent time to market and test quality.

66 citations


Cited by
More filters
Journal ArticleDOI
Subhasish Mitra1, N. Seifert1, Ming Zhang1, Quan Shi1, Kee Sup Kim1 
TL;DR: A new design paradigm reuses design-for-testability and debug resources to eliminate transient errors caused by terrestrial radiation in chip designs.
Abstract: Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

600 citations

Proceedings ArticleDOI
01 Sep 2003
TL;DR: This paper discusses the prac- tical issues associated with power consumption during at-speed tests, and delineates in more detail the nature of power-related phenomena encountered in structured speed tests.
Abstract: At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.

404 citations

Journal ArticleDOI
TL;DR: The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design- for-testability and design-for-debug resources to minimize area overheads.
Abstract: This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

226 citations

Proceedings ArticleDOI
W. Needham1, C. Prunty1, Eng Hong Yeoh1
18 Oct 1998
TL;DR: In this paper, defects found in a high volume microprocessor when shipping at a low defect level are explored to forecast the need for better tools and methods to earlier achieve high quality goals.
Abstract: This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM is covered. Three defective devices are then root cause analyzed for defect type, electrical effect and possible ways to screen earlier in the device life cycle or manufacturing process. The implications of these defects along with process trends are used to forecast the need for better tools and methods to earlier achieve high quality goals.

203 citations

Journal ArticleDOI
TL;DR: The system presented here consists of an on-chip debug infrastructure and supporting debugger software, which interacts with the infrastructure to make the chip's features accessible through a serial interface.
Abstract: For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chip's features accessible through a serial interface.

184 citations