Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical devices. The basics of wafer-bonding technology are described, including microcleanroom approaches, prevention of interface bubbles, bonding of III-V compounds, low-temperature bonding, ultra-high vacuum bonding, thinning methods such as smart-cut procedures, and twist wafer bonding for compliant substrates. Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.

Semiconductor wafer bonding

This paper provides a detailed overview of developments in transducer materials technology relating to their current and future applications in micro-scale devices. Recent advances in piezoelectric, magnetostrictive and shape-memory alloy systems are discussed and emerging transducer materials such as magnetic nanoparticles, expandable micro-spheres and conductive polymers are introduced. Materials properties, transducer mechanisms and end applications are described and the potential for integration of the materials with ancillary systems components is viewed as an essential consideration. The review concludes with a short discussion of structural polymers that are extending the range of micro-fabrication techniques available to designers and production engineers beyond the limitations of silicon fabrication technology.

/pdf/new-materials-for-micro-scale-sensors-and-actuators-an-21qnaonn0l.pdf

New materials for micro-scale sensors and actuators An engineering review

Wafer-to-wafer bonding processes for microstructure fabrication are categorized and described. These processes have an impact in packaging and structure design. Processes are categorized into direct bonds, anodic bonds, and bonds with intermediate layers. Representative devices using wafer-to-wafer bonding are presented. Processes and methods for characterization of a range of bonding methods are discussed. Opportunities for continued development are outlined.

/pdf/wafer-to-wafer-bonding-for-microstructure-formation-5fhi80w5zw.pdf

Wafer-to-wafer bonding for microstructure formation

It is a well-known phenomenon that two solids with sufficiently flat surfaces can stick to each other when brought into intimate contact in ambient air at room temperature. The attraction between the two bodies is primarily mediated through van der Waals forces or hydrogen bonding. Without a subsequent heating step, that type of bonding is reversible. Annealing may increase the energy of adhesion up to the cohesive strength of the materials concerned. The wafer bonding phenomena in brittle materials systems, especially in silicon, is reviewed in the experiment. The focus is on low temperature bonding techniques. The pivotal influence chemical species on the surfaces have on the subsequent type of bonding (van der Waals, hydrogen, covalent bonding, mechanical interlocking) is discussed. Methods of modifying the surface chemistry for tailoring bonding properties are addressed. The paper is aimed at providing an overview of the current understanding of the factors determining the bondability and strength of the bonding obtainable. The authors assess the present state of the experimental methods for determining basic parameters governing the adhesion. A number of examples illustrate the applicability of fusion bonding for as diverse fields as opto-electronics, microsystems technology, and fabrication of advanced substrates like silicon-on-insulator wafers.

/pdf/wafer-direct-bonding-tailoring-adhesion-between-brittle-zsnabx6cpy.pdf

Wafer direct bonding: tailoring adhesion between brittle materials

Several aspects of a new silicon‐on‐insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face‐to‐face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10‐s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal‐oxide‐semiconductor (MOS) capacitors. The results were consistent with a negative charge de...

Bonding of silicon wafers for silicon‐on‐insulator

The microwave performance of 1- mu m gate-length n-MOSFETs fabricated on both SIMOX and BESOI substrates was measured. The process included a self-aligned silicide in an otherwise conventional MOS sequence. Initial optimization yielded devices with an f/sub max/ of 14 GHz on BESOI and 11 GHz on SIMOX. Coplanar waveguides (CPWs) were fabricated on substrates with resistivities from 4 to 4000 Omega -cm. A loss of 1.8 dB/cm at 2 GHz was demonstrated on the 4000- Omega -cm float-zone substrate. >

Microwave performance of SOI n-MOSFETs and coplanar waveguides

A model for small-signal dynamic self-heating is derived for the general case of a two-port device and then specialized to the case of an SOI MOSFET. The model is fitted to measured data for an SOI MOSFET and shown to accurately describe the frequency dependence of the self-heating. For this device, three time constants of 0.25 mu s, 17 ns, and 90 ps adequately characterize the thermal response, showing that self-heating effects are active over a very wide frequency range. >

Linear dynamic self-heating in SOI MOSFETs

A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm/sup 2/ at room temperature to approximately=2200 erg/cm/sup 2/ at 1400 degrees C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800 degrees C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10/sup 11/ cm/sup -2/. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3- mu m-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 mu s in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was >

Silicon-on-insulator by wafer bonding and etch-back

This paper presents a large-signal SOI MOSFET model which explicitly includes self-heating effects. Our goal is to develop a model suitable for SOI monolithic microwave IC (MMIC) design which clearly requires a large-signal model accurate at high frequencies. In addition, the model must include the dynamic thermal response of the device since MMICs often contain microwave, RF, baseband, and bias sections spanning the range from DC to several GHz. At DC, self-heating can be modeled with a simple thermal resistance, while at microwave frequencies the temperature is effectively constant. However, at intermediate frequencies the temperature lags the applied power so the model must accurately represent the thermal dynamics in the device.

http://ieeexplore.ieee.org/iel3/4044/11594/00526438.pdf

A. Caviglia

Papers

Bonding of silicon wafers for silicon‐on‐insulator

Microwave performance of SOI n-MOSFETs and coplanar waveguides

Linear dynamic self-heating in SOI MOSFETs

Silicon-on-insulator by wafer bonding and etch-back

A large-signal model for SOI MOSFETs including dynamic self-heating effects