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A. Dmitriev

Bio: A. Dmitriev is an academic researcher from Saint Petersburg State University. The author has contributed to research in topics: Boolean circuit & Combinational logic. The author has an hindex of 3, co-authored 4 publications receiving 62 citations.

Papers
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Proceedings ArticleDOI
28 Apr 1996
TL;DR: Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper and the usefulness of the proposed method is demonstrated for MCNC benchmark circuits.
Abstract: Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper This method is based on the newly introduced concept of a self-dual complement of a given Boolean function The parity prediction function f/sub p/ of ordinary parity checking is replaced by the self-dual complement /spl delta//sub p/ of this function such that the module-2 sum of the outputs of the monitored circuit and of /spl delta//sub p/ is an arbitrary self-dual Boolean function h Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement /spl delta//sub p/ is small Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs The fault coverage of this method is almost the same as for parity checking The usefulness of the proposed method is demonstrated for MCNC benchmark circuits

32 citations

Proceedings ArticleDOI
02 Dec 1998
TL;DR: A new method for the implementation of a self-dual circuit with alternating inputs that is especially useful for online testing of control systems for which time is not critical is proposed.
Abstract: In this paper we propose a new method for the implementation of a self-dual circuit with alternating inputs. For every circuit output the self-dual complement is designed. Contrary to ordinary duplication and comparison the corresponding self-dual complements and the monitored circuit itself can be jointly, implemented. The self-dual duplicated circuits can be used in test mode, online mode and in fast mode without alternating inputs. Because of the necessary time redundancy, the approach is especially useful for online testing of control systems for which time is not critical.

15 citations

Proceedings ArticleDOI
03 Jul 2000
TL;DR: The new method of concurrent checking is developed for the concrete case of 1-out-of-4 codes and it is shown that for an arbitrarily given combinational circuit f an additional complementary circuit g is determined.
Abstract: In this paper a new method for concurrent checking is proposed. For an arbitrarily given combinational circuit f an additional complementary circuit g is determined such that for every input the componentwise modulo 2 sum of the corresponding outputs of f and g is an element of a considered cone as long as no error occurs. The new method of concurrent checking is developed for the concrete case of 1-out-of-4 codes.

14 citations

Journal ArticleDOI
TL;DR: In this paper new methods for the transformation of a given combinational circuit into a self-dual circuit based on the notion of a self,dual complement are investigated and for the first time it is described in this paper how aself-duAL circuit can be modified into aSelf- dual fault-secure circuit.
Abstract: In this paper new methods for the transformation of a given combinational circuit into a self-dual circuit based on the notion of a self-dual complement are investigated. The large variety of self-dual complements can be utilized to optimize the transformed self-dual circuit. Self-dual duplication and self-dual parity prediction are considered in detail. As a method for the reduction of self-dual outputs, output space compaction of self-dual outputs is considered. For the first time we also describe in this paper how a self-dual circuit can be modified into a self-dual fault-secure circuit.

2 citations


Cited by
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Journal ArticleDOI
TL;DR: An overview of a comprehensive collection of on-line testing techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.
Abstract: This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

234 citations

Proceedings ArticleDOI
24 Oct 2001
TL;DR: These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency.
Abstract: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.

110 citations

Journal ArticleDOI
TL;DR: It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads, so for large values of m these overheads are particularly low.
Abstract: In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads. These hardware overheads are generally independent of m and comprise only a handful of gates, so for large values of m these overheads are particularly low. The fault coverage of the presented structures has been investigated by simulation experiment and shown to range between 90% and 94.3%.

66 citations

Proceedings ArticleDOI
10 Mar 2008
TL;DR: The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.
Abstract: This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error detection (CED) based on such circuits is described in this paper. CED based on approximate logic circuits does not impose any performance penalty on the original design. The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.

63 citations

Proceedings ArticleDOI
01 May 2005
TL;DR: Results indicate significant reductions in area overhead due to the new code selection procedure as well as the ability to find low power implementations for use in power conscious applications.
Abstract: An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code followed by structure constrained logic optimization that produces a circuit in which all single point faults are guaranteed to be detected. Two new contributions over previous work include (1) the use of a k-way partitioning algorithm combined with local search to select a parity-check code, and (2) a methodology for minimizing power consumption in the CED circuitry. Results indicate significant reductions in area overhead due to the new code selection procedure as well as the ability to find low power implementations for use in power conscious applications.

42 citations