A.K. Gupta

Bio: A.K. Gupta is an academic researcher from Ottawa University. The author has contributed to research in topics: Asynchronous Transfer Mode & Head-of-line blocking. The author has an hindex of 2, co-authored 2 publications receiving 45 citations.

16*16 limited intermediate buffer switch module for ATM networks

Abstract: An investigation is made of the performance of a nonblocking packet switch having input buffers and a limited amount of buffers within the switch fabric, where contention for the output ports occurs. This technique improves the performance significantly, while maintaining the switch fabric speed equal to that of the port speed. For uniform traffic, a 16*16 switch with head of line priority scheduling has an achievable throughput equal to 87.5%. The simulation results suggest that for unbalanced and bursty traffic, the performance of the switch does not degrade appreciably. >

Limited intermediate buffer switch modules and their interconnection networks for B-ISDN

Abstract: Gupta et al. (1991) presented an analysis of a limited intermediate buffer (LIB) switch consisting of input buffers and a limited amount of buffers in the switch fabric, where contention for the output ports occurs. A novel scheduling scheme based on head of line blocking was proposed, which improved the performance significantly. For uniform random traffic, a 16*16 LIB switch had an achievable throughput equal to 87.5%. The authors examine the switch performance under two delay dependent priority classes and show that the achievable throughput can be increased to 91%. To build large-size switching systems, a multistage interconnection network is proposed, which meets the demands of large-scale asynchronous transfer mode (ATM) switch design, such as (1) modularity, (2) relaxed synchronization, (3) guaranteed high performance without requiring internal speedup, and (4) maintaining packet sequence integrity. The simulation results of three-stage interconnection networks prove the efficacy of the LIB switch architecture and the proposed scheduling scheme. >

CIXB-1: combined input-one-cell-crosspoint buffered switch

Abstract: Buffered crossbars have been considered as an alternative for non-buffered crossbars to improve switching throughput. The drawback of a buffered crossbar is the memory amount that is proportional to the square of the number of ports (O(N/sup 2/)). This is not the main limitation when the buffer size is kept to a minimum size such that implementation is feasible. For a small buffer size, the number of ports of a switch module is not limited by the memory amount but by the pin count. We propose a novel architecture: a combined input-one-cell-crosspoint buffer crossbar (CIXB-1) with virtual output queues (VOQs) at the inputs and round-robin arbitration. We show that the proposed architecture can provide 100% throughput under uniform traffic. A CIXB-1 offers several advantages for a feasible implementation such as scalability and timing relaxation. With the currently available memory technology, a one-cell-crosspoint buffered switch is feasible for a 32/spl times/32 fabric module.

Survey of ATM switch architectures

Abstract: For reasons of economy and flexibility, BISDN (Broadband Integrated Services Digital Network) is expected to replace existing application-oriented communication networks. ATM (Asynchronous Transfer Mode) is a high-speed packet-switching technique that has emerged as the most promising technology for BISDN. Since early 1980s, a large number of architectures have been proposed for ATM switching. In this paper, we present a descriptive survey of ATM switch architectures, with emphasis on electronic space-division point-to-point switches.

CIXOB-k: combined input-crosspoint-output buffered packet switch

Abstract: We propose a novel architecture, a combined input-crosspoint-output buffered (CIXOB-k, where k is the size of the crosspoint buffer) Switch. CIXOB-k architecture provides 100% throughput under uniform and unbalanced traffic. It also provides timing relaxation and scalability. CIXOB-k is based on a switch with combined input-crosspoint buffering (CIXB-k) and round-robin arbitration. CIXB-k has a better performance than a non-buffered crossbar that uses iSLIP arbitration scheme. CIXOB-k uses a small speedup to provide 100% throughput under unbalanced traffic. We analyze the effect of the crosspoint buffer size and the switch size under uniform and unbalanced traffic for CIXB-k. We also describe solutions for relaxing the crosspoint memory amount and scalability for a CIXOB-k switch with a large number of ports.

MCBF: a high-performance scheduling algorithm for buffered crossbar switches

Abstract: The buffered crossbar architecture is becoming very attractive for the design of high performance routers due the unique features it offers. Many distributed scheduling algorithms have been proposed for this architecture. Despite their distributed nature, the existing schemes require quite a bit of hardware and timing complexity. We propose a novel scheduling scheme named the most critical buffer first (MCBF). This scheme is based only on the internal buffer information and requires much less hardware than the existing schemes. Yet, it exhibits good performance and outperforms all its competitors. More interestingly, MCBF shows optimal stability performance while being almost a stateless algorithm.

An evolution to crossbar switches with virtual output queuing and buffered cross points

Abstract: Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high speeds and have been a subject of intense research in the past decade. VOQ IQ switches require switch matrix scheduling algorithms to match input ports to out ports. In this tutorial article, we present an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics. We then describe what we believe will be the next generation of high-speed crossbar switches: the evolution of IQ switches to combined input and crossbar queued (CICQ) switches. With the continued increase in density of VLSI, sufficient buffering at crossbar cross points for one cell or packet has become feasible to implement. We show how CICQ switches have simple schedulers and result in lower delay than IQ switches. Both IQ and CICQ switches have unstable regions. We show how a threshold and bursting technique can feasibly achieve stability. We also show how CICQ switches are better suited (than IQ switches) for switching of variable-length packets such as IP packets. Many challenges remain in IQ and CICQ switches. In particular, the inclusion of QoS scheduling methods that are currently only suitable for output queued switches is a major open problem.