A.M. Davis

Bio: A.M. Davis is an academic researcher from San Jose State University. The author has contributed to research in topics: Electronics & Integrated circuit packaging. The author has an hindex of 1, co-authored 1 publications receiving 377 citations.

Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators

Abstract: This work demonstrates multistage complementary NOR, OR, NAND, and AND logic gates and ring oscillators (frequency ∼220 Hz) with arrays of p- and n-type nanotube field effect transistors (FETs). The demonstration is made possible by progress in three aspects of nanotube synthesis and integration. First, patterned growth leads to large numbers of nanotube FETs in an array, as up to 70% of individual nanotubes are semiconductors. Second, metal electrodes are successfully embedded underneath nanotubes and used as local gates. Third, complementary logic gates are made possible by converting p-type FETs in an array into n-type FETs by a local electrical manipulation and doping approach.

Ion-sensitive field-effect transistor for biological sensing

Abstract: In recent years there has been great progress in applying FET-type biosensors for highly sensitive biological detection. Among them, the ISFET (ion-sensitive field-effect transistor) is one of the most intriguing approaches in electrical biosensing technology. Here, we review some of the main advances in this field over the past few years, explore its application prospects, and discuss the main issues, approaches, and challenges, with the aim of stimulating a broader interest in developing ISFET-based biosensors and extending their applications for reliable and sensitive analysis of various biomolecules such as DNA, proteins, enzymes, and cells.

Active capacitor multiplier in Miller-compensated circuits

Abstract: A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit. Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or BiCMOS. Furthermore, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1-/spl mu/m BiCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 /spl Omega/, and load capacitors ranging from 1.5 nF to 20 /spl mu/E The total quiescent current flowing through the regulator was less than 30 /spl mu/A during zero load-current conditions.

Triple-mode single-transistor graphene amplifier and its applications.

Abstract: We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.