A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Method and system for storage of data in non-volatile media

Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We show in particular that any planar graph of n vertices has an O(n lg2 n) area layout and that any tree of n vertices can be laid out in linear area. The algorithm maintains a sparse representation for layouts that is based on the well-known UNION-FIND data structure, and as a result, the running time devoted to bookkeeping is nearly linear.

Area-efficient graph layouts

A pyramidal data processing system comprising a plurality of levels of processor arrays, the number of processors in an array increases in number from a level of lowest resolution to a level of highest resolution. Each processor in an array is coupled for data transfer to a neighborhood of processors including laterally and diagnoally adjacent processors in the same level, a processor in the level of next lowest resolution, and processors in the level of next greatest resolution. A memory is associated with each processor to store value of data elements. A controller and control memory generate control signals to perform in synchrony data transformations on selected data elements associated with each neighborhood of processors.

Data processing system having a pyramidal array of processors

A network of computing nodes is connected by communication channels into fully-interconnected units and groups of units. Each unit has one and only one direct connection to each other unit in a group, and any one computing node in any unit has a direct connection to at most one other unit. The nodes are suitably computing networks themselves so there can be any number of levels of recursion. In a method of routing and transferring information, each node is given an address having address portions respectively identifying its location at each level of recursion. The information is sent from that port of the sending node which has a port identification identical to the highest order address portion in the destination address which is different from the corresponding address portion of the sending computing node. Each computing node suitably has processing assemblies each having a digital processor, first and second memories, partitioning circuitry, and assembly control circuitry, communicating on a common intranodal shared bus. Each assembly is a port to an external bus. Each digital processor is able to communicate the information it generates from its first memory through the partitioning circuitry to a bus simultaneously with the partitioning circuitry also permitting access by other information to the second memory along the other bus.

Apparatus, methods, and systems for computer information transfer

In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one milion transistors to the various functional blocks is given, and the result is a memory intensive design.

Design Considerations for Single-Chip Computers of the Future

A communication network for a tree-structured assembly (X-TREE) of single-chip processors is described, and considerations for selecting this particular approach are discussed. The communication links between the processors are high-speed, byte-parallel connections with an asynchronous handshaking protocol. Each node of X-TREE consists of a powerful processor, a switching network and a dedicated communications controller. The latter checks the availability of the links terminating in this node, supervises the creation and elimination of message channels and controls the routing and time multiplexing of concurrent messages over the same link. The switching network inside each X-NODE connects the external links with the internal processor via a fast multiplexed bus which is interfaced to each input/output port through fifo message buffers. Network topology, routing algorithm, addressing scheme, message format and communication hardware are discussed.

Communication In X-TREE, A Modular Multiprocessor System

The construction of Fast Fourier Transform (FFT) processors is discussed. Pipeline and parallel-pipeline organizations are developed and are shown to meet the constraints imposed by VLSI. Various circuit technologies for the construction of these processors are compared, and the description of a set of NMOS chips are given. A technique for reducing the latency of the adders internal to the chips is also presented. Finally, a broad set of possible FFT organizations is discussed.

A. M. Despain

Papers

Communication In X-TREE, A Modular Multiprocessor System

VLSI implementation of digital fourier transforms