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A. M. Francis

Bio: A. M. Francis is an academic researcher from University of Arkansas. The author has contributed to research in topics: CMOS & Comparator. The author has an hindex of 9, co-authored 13 publications receiving 274 citations.

Papers
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Journal ArticleDOI
TL;DR: In this article, a single event model capable of capturing bias-dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit.
Abstract: A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

142 citations

Journal ArticleDOI
TL;DR: In this article, a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2-μm silicon carbide (SiC) CMOS process are described.
Abstract: This paper describes a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2- $\mu \text{m}$ silicon carbide (SiC) CMOS process. These circuits are used as building blocks for designing a high-temperature SiC low-side over current protection circuit. The over current protection circuit is used in the protection circuitry of a SiC FET gate driver in power converter applications. The op-amp and the comparator have been tested at 400 °C and 550 °C temperature, respectively. The op-amp has an input common-mode range of 0–11.2 V, a dc gain of 60 dB, a unity gain bandwidth of 2.3 MHz, and a phase margin of 48° at 400 °C. The comparator has a rise time and a fall time of 38 and 24 ns, respectively, at 550 °C. The over current protection circuit, implemented with these analog building blocks, is designed to sense a voltage across a sense resistor up to 0.5 V.

40 citations

Journal ArticleDOI
TL;DR: In this paper, a pair of high-temperature voltage and current references have been designed in a silicon carbide CMOS process and tested to 300 °C under probe and 540 °C in a packaged form.
Abstract: This paper presents a pair of high-temperature voltage and current references that have been designed in a silicon carbide CMOS process. The circuits presented have been fabricated in two fabrication runs and tested to 300 °C under probe and 540 °C in a packaged form. Test results over a single wafer at multiple sites are given to provide variation over process data. The circuits include a voltage reference with an accuracy of better than 100 ppm/°C and a constant current reference with a variation of $\pm 1~\mu \text{A}$ at a nominal output of 11 $\mu \text{A}$ from 25 °C to 540 °C.

29 citations

Proceedings ArticleDOI
01 Nov 2015
TL;DR: In this article, the first operational digital to analog converter at 400°C was presented, which was designed in the Raytheon 1.2 μm CMOS HiTSiC process.
Abstract: This paper presents the first operational digital to analog converter at 400°C. The 8 bit R-2R ladder DAC was designed in the Raytheon 1.2 μm CMOS HiTSiC process. The data converter is also the first of its kind in SiC. It has been tested with a supply voltage between 12 V and 15 V, and reference voltages of 5 V to 8 V. At 400°C, the maximum measured differential non linearity (DNL) is 2 LSB (least significant bit) and the integral non linearity is 4.4 LSB.

17 citations

Journal ArticleDOI
TL;DR: Bias-dependent models are shown to more accurately predict expected physical observations and Technology Computer Aided Design (TCAD) simulation, especially when such charge-sharing upsets must be considered.
Abstract: When evaluating sub-100 nm circuits for hardness to Single Event Transients (SETs), the choice of strike model is shown to have a notable effect upon observed upsets. A method utilizing distributed charges to model strikes to adjacent devices is illustrated and utilized to compare the effect of strike kernel models in such Charge Sharing SETS (CSSETS). Bias-dependent models are shown to more accurately predict expected physical observations and Technology Computer Aided Design (TCAD) simulation, especially when such charge-sharing upsets must be considered.

16 citations


Cited by
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Journal ArticleDOI
TL;DR: A review of digital single event transient research can be found in this paper, including a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a state-of-the-art in SET testing and modelling, and a discussion of the impact of technology scaling trends on future SET significance.
Abstract: The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

309 citations

Journal ArticleDOI
TL;DR: In this article, a single event model capable of capturing bias-dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit.
Abstract: A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

142 citations

Journal ArticleDOI
TL;DR: Part I reviewed compact models for silicon carbide (SiC) power diodes and MOSFETs and part II completes the review of SiC devices and covers gallium nitride devices as well.
Abstract: Wide bandgap power devices have emerged as an often superior alternative power switch technology for many power electronic applications. These devices theoretically have excellent material properties enabling power device operation at higher switching frequencies and higher temperatures compared with conventional silicon devices. However, material defects can dominate device behavior, particularly over time, and this should be strongly considered when trying to model actual characteristics of currently available devices. Compact models of wide bandgap power devices are necessary to analyze and evaluate their impact on circuit and system performance. Available compact models, i.e., models compatible with circuit-level simulators, are reviewed. In particular, this paper presents a review of compact models for silicon carbide power diodes and MOSFETs.

115 citations

Journal ArticleDOI
01 Aug 2021
TL;DR: In this article, the authors report the monolithic integration of enhancementmode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits.
Abstract: Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. Through the monolithic integration of enhancement-mode n-type and p-type gallium nitride field-effect transistors, complementary integrated circuits including latch circuits and ring oscillators can be created for use in high-power and high-frequency applications.

97 citations

Journal ArticleDOI
TL;DR: A simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations, and the results illustrate why a conventional model based on one double-exponential source can be incomplete.
Abstract: Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. An accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. A small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. The parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.

86 citations