In this work the proton irradiation influence on Multiple Gate MOSFETs (MuGFETs) performance is investigated. This analysis was performed through basic and analog parameters considering four different splits (unstrained, uniaxial, biaxial, uniaxial+biaxial). Although the influence of radiation is more pronounced for p-channel devices, in pMuGFETs devices, the radiation promotes a higher immunity to the back interface conduction resulting in the analog performance improvement. On the other hand, the proton irradiation results in a degradation of the post-irradiated n-channel transistors behavior. The unit gain frequency showed to be strongly dependent on stress efficiency and the radiation results in an increase of the unit gain frequency for splits with high stress effectiveness for both cases p- and nMuGFETs.

Influence of 60-MeV Proton-Irradiation on Standard and Strained n- and p-Channel MuGFETs

In this work the proton irradiation influence on basic and analog parameters of triple-gate SOI MOSFETs is investigated. The studied devices are strained and unstrained p- and nMuGFETs. The type of stress considered in each case, was the stress that results in a better performance of p- (CESL) and n-devices (sSOI+CESL). Although the results showed the worse behavior for post-irradiated nMOS transistors, a higher immunity to the back interface influence was obtained for post-irradiated pMOS devices and consequently a better analog performance was observed. The unit gain frequency improved for p and nMOS post-irradiated devices.

Impact of proton irradiation on strained triple gate SOI p- and n-MOSFETs

A simplified analytical approach within the framework of Landauer-Buttiker formalism has been employed to model the drain current in a ballistic n-channel metal oxide semiconductor field effect transistor (MOSFET) and the expression for the device threshold voltage has been obtained. To achieve ballistic operation the said MOSFET has been modeled considering low temperature (77 K) and intrinsic silicon channel for electronic motion of the charge carriers. The model incorporates quantum confinement effect, drain induced barrier lowering (DIBL) and short channel effects (SCE). Further, the effects due to surface scattering and back scattering are included in this model to obtain a near ballistic behavior. The current-voltage characteristics are compared with the available experimental results and are found to be in reasonable agreement.

Analytical Model for Drain Current of a Ballistic MOSFET

Among the potential candidates for replacement of SiO/sub 2/ or SiO/sub x/N/sub y/ as gate dielectric, HfO/sub 2/ seems to be one of the most promising materials, combining high dielectric permittivity with low leakage current due to a reasonably high barrier height that limits electron tunneling (Peacock and Robertson, 2004). Other requirements on gate dielectric materials like low density of interface states, gate compatibility, structural, physical and chemical stability at both gate electrode/dielectric and dielectric/silicon interfaces are currently making the object of intensive investigation for sub 0.1 /spl mu/m channel length devices using high-k dielectrics. The transition layer becomes important in such dielectrics in deciding the device performance. In this paper, we discuss the scaling limits of HfO/sub 2//SiO/sub 2/ stacked dielectrics taking into consideration the impact of transition layer between HfO/sub 2/ and SiO/sub 2/. In this paper, analysis of HfO/sub 2//SiO/sub 2/ gate dielectric stack has been carried out for replacement of SiO/sub 2/ using an appropriate direct-tunneling gate-current model. It has the potential to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

A. Madan

Papers

Evaluation of device parameters of HfO/sub 2//SiO/sub 2//Si gate dielectric stack for MOSFETs