Bio: A. Martin is an academic researcher from University College Cork. The author has contributed to research in topics: Gate oxide & Breakdown voltage. The author has an hindex of 6, co-authored 17 publications receiving 164 citations.
TL;DR: A review of the most common dielectric reliability measurement methods can be found in this paper, where a broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified.
Abstract: Reliability of thin dielectric films such as silicon dioxide grown on single crystalline silicon is of great importance for integrated circuits of present and future technologies. For the characterization of the quality of dielectric films, it is essential to have measurement methods available which can give a measure of dielectric reliability in a relatively short time. Stress biases are usually highly accelerated and cause destructive dielectric breakdown. Testing for dielectric reliability has been performed for more than 30 years, and in that time many different stress methods have been established. This article reviews that most common dielectric reliability measurement methods and gives practical guidelines to the reliability engineer in the field of dielectric characterization. The examples and data shown here are mainly from MOS gate oxides. The aim of this review paper is to emphasize advantages and disadvantages of the various stress methods. Appropriate dielectric stress methods are pointed out for applications such as process development, process characterization, pocess control and screening (burn-in). A broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified. Suitable dielectric test structures and the determination of the correct voltage and thickness of the dielectric are discussed; they are essential to determine the electric field across the thin film. The identification of dielectric breakdown and the interpretation and significance of the measurement results are reviewed. A good understanding of the stress method and the various measured parameters is essential to draw correct conclusions for the lifetime of the dielectric at operating conditions. The commonly used, basic analysis techniques for the measurement results are illustrated. Finally, the influence of stress-induced leakage currents on the dielectric reliability characterization is discussed and other aspects relating to very thin oxides of future technologies are briefly described. The paper also includes a large bibliography of more than 250 references.
••31 Dec 1996
TL;DR: In this paper, voltage and current stress measurements in the Fowler-Nordheim regime, performed on gate oxides (9 nm-28 nm), indicated that a ramped pre-stress prior to a constant stress can increase the time to breakdown in some cases.
Abstract: In this study, voltage and current stress measurements in the Fowler-Nordheim regime, performed on gate oxides (9 nm-28 nm), indicated that a ramped pre-stress prior to a constant stress can increase the time to breakdown in some cases. In the literature oxide breakdown is said to be related to a fixed amount of trapped oxide charge or to a fixed amount of generated traps in the oxide. However, these models cannot explain our experimental observations. Current-time, current-charge, voltage-time characteristics and results of high frequency pre-stresses have been extensively studied in order to gain information about the charge trapping properties of the virgin and pre-stressed oxides. It is concluded from experimental results that the rate of initial positive charge build up in the oxide during the constant stress is a key factor for oxide degradation and breakdown.
TL;DR: In this paper, the authors compared the times to breakdown of RVS and CVS for thermally grown oxides on single crystal and on polycrystalline silicon and found that RVS has the advantage over CVS of recording the breakdown properties in a very fast time and is therefore widely used in industry.
Abstract: This paper investigates constant voltage stress (CVS) and ramped voltage stress (RVS) for thermally grown oxides on single crystal and on polycrystalline silicon. CVS is a standard stress for the measurement and prediction of oxide lifetimes. However, RVS has the advantage over CVS of recording the breakdown properties in a very fast time and is, therefore, widely used in industry. The aim of this work is the assessment of a correlation between times to breakdown of RVS and CVS. Times to breakdown of RVS and CVS are compared directly and it has been found that they do not correlate with a simple classical model. An anomaly is reported for thick oxides grown on polycrystalline silicon: greater breakdown voltages are recorded for slow ramps than for fast ramps. It is shown that the times to breakdown which are estimated from RVS are longer than times to breakdown of CVS. The increase in times is dependent on the oxide thickness. This is verified with CVS measurements on pre-stressed oxides. In contradiction to the literature, results from pre-stressed oxides were found to have greater time to breakdown and charge to breakdown values than data of virgin oxides. The results of this work give evidence that the time to breakdown and the injected charge to breakdown of the voltage stress measurements are strongly influenced by charge trapping effects in the oxide layer. Longer times to breakdown resulting from a RVS have to be taken into account when lifetimes at use conditions are predicted from RVS results. If this is not considered oxide lifetimes at operating voltage will be overestimated.
16 Oct 1994
TL;DR: In this article, the effect of ramped voltage stress (RVS) on oxide lifetimes was investigated for six oxides which had been thermally grown from polysilicon, and the results showed that RVS increases oxide lifetime and the current-time characteristics were studied to find the cause of the increased RVS lifetimes.
Abstract: Accelerated stress measurements such as constant voltage stress (CVS) and ramped voltage stress (RVS) are commonly used in industry for the evaluation of oxide lifetimes. The main advantage of RVS over CVS is the short measurement time. Therefore, RVS is widely used, especially, in short dielectric screens and, lifetimes are extrapolated from the RVS measurement results. For this lifetime extrapolation a correlation between RVS data and CVS lifetimes is assumed. This correlation between CVS and RVS results is investigated for six oxides which had been thermally grown from polysilicon. CVS and RVS measurements were performed over a wide range of bias conditions and the measurement results were directly compared. This comparison showed that RVS increases oxide lifetimes. The current-time characteristics were studied in order to find the cause of the increased RVS lifetimes. They indicated lower currents for RVS than for CVS at equal bias voltage levels. Further measurements were carried out to study the effect of a RVS prior to CVS. Findings from these measurements with pre-stressed oxides confirmed the RVS lifetime increase which had been seen earlier. The increase in RVS lifetimes is critical for the prediction of oxide lifetimes at operating voltage. This increase has to be taken into account when lifetimes are predicted from RVS results. If it is not oxide lifetimes will be overestimated.
22 Oct 1995
TL;DR: In this paper, the authors compared the time to breakdown distributions of MOS gate oxides which were stressed with a constant voltage (or current) stress or a pre-stressing voltage/current ramp followed by a constant volt/current stress.
Abstract: In this study time to breakdown distributions are compared for MOS gate oxides which were stressed with a constant voltage (or current) stress or a pre-stressing voltage (or current) ramp followed by a constant voltage (or current) stress. Results show clearly that a pre-stress can increase time to breakdown. This increase is discussed and it is shown that it is dependent on oxide thickness, pre-stressing ramp rate and the processing conditions. The current-time (or voltage-time) characteristics of the constant stress are investigated and it is observed that charge trapping in the oxide is the reason for the time to breakdown increase. The pre-stressed oxide clearly shows a different initial charge trapping characteristic than the non prestressed oxide. The measurement results are discussed and it is demonstrated that the common understanding of oxide breakdown cannot explain the observed results. Therefore, a new parameter is proposed which is related to oxide degradation and breakdown and which has to be considered in combined ramped/constant stress measurements.
TL;DR: In this paper, the authors focus on the case of gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm.
Abstract: In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...
TL;DR: In this paper, the authors provide an overview of the underlying physics behind connectivity changes in highly conductive regions under an electric field, and discuss percolation model approaches and the theory for the scaling behaviors of numerous transport properties observed in RS.
Abstract: Resistive switching (RS) phenomena are reversible changes in the metastable resistance state induced by external electric fields. After discovery ∼50 years ago, RS phenomena have attracted great attention due to their potential application in next-generation electrical devices. Considerable research has been performed to understand the physical mechanisms of RS and explore the feasibility and limits of such devices. There have also been several reviews on RS that attempt to explain the microscopic origins of how regions that were originally insulators can change into conductors. However, little attention has been paid to the most important factor in determining resistance: how conducting local regions are interconnected. Here, we provide an overview of the underlying physics behind connectivity changes in highly conductive regions under an electric field. We first classify RS phenomena according to their characteristic current–voltage curves: unipolar, bipolar, and threshold switchings. Second, we outline the microscopic origins of RS in oxides, focusing on the roles of oxygen vacancies: the effect of concentration, the mechanisms of channel formation and rupture, and the driving forces of oxygen vacancies. Third, we review RS studies from the perspective of statistical physics to understand connectivity change in RS phenomena. We discuss percolation model approaches and the theory for the scaling behaviors of numerous transport properties observed in RS. Fourth, we review various switching-type conversion phenomena in RS: bipolar-unipolar, memory-threshold, figure-of-eight, and counter-figure-of-eight conversions. Finally, we review several related technological issues, such as improvement in high resistance fluctuations, sneak-path problems, and multilevel switching problems.
TL;DR: In this paper, the recent developments of (Ba,Sr)TiO 3 (BST) thin films for future Gbit era dynamic random access memory (DRAM) applications are reviewed.
Abstract: This paper reviews the recent developments of (Ba,Sr)TiO 3 (BST) thin films for future Gbit era dynamic random access memory (DRAM) applications. The trends of DRAM capacitors in the last decade are briefly described first. Then the technological aspects of BST films such as deposition techniques, post-annealing, physical, electrical and dielectric characteristics of the films, effects of electrode materials, dielectric relaxation and defect analysis and the reliability phenomena associated with the films are briefly reviewed with specific examples from recent literature. The basic mechanisms that control the bulk electrical conduction and the origin of leakage currents in BST films are also discussed. Finally, possible developments of gigabit era DRAM technology are summarized.
TL;DR: In this paper, the authors studied leakage currents and dielectric breakdown in MIS capacitors of metal-aluminum oxide-silicon (AlN) with a thickness and structure that depended on the process time and temperature.
Abstract: Leakage currents and dielectric breakdown were studied in MIS capacitors of metal-aluminum oxide-silicon. The aluminum oxide was produced by thermally oxidizing AlN at 800-1160/spl deg/C under dry O/sub 2/ conditions. The AlN films were deposited by RF magnetron sputtering on p-type Si (100) substrates. Thermal oxidation produced Al/sub 2/O/sub 3/ with a thickness and structure that depended on the process time and temperature. The MIS capacitors exhibited the charge regimes of accumulation, depletion, and inversion on the Si semiconductor surface. The best electrical properties were obtained when all of the AlN was fully oxidized to Al/sub 2/O/sub 3/ with no residual AlN. The MIS flatband voltage was near 0 V, the net oxide trapped charge density, Q/sub 0x/, was less than 10/sup 11/ cm/sup -2/, and the interface trap density, D/sub it/, was less than 10/sup 11/ cm/sup -2/ eV/sup -1/, At an oxide electric field of 0.3 MV/cm, the leakage current density was less than 10/sup -7/ A cm/sup -2/, with a resistivity greater than 10/sup 12/ /spl Omega/-cm. The critical field for dielectric breakdown ranged from 4 to 5 MV/cm. The temperature dependence of the current versus electric field indicated that the conduction mechanism was Frenkel-Poole emission, which has the property that higher temperatures reduce the current. This may be important for the reliability of circuits operating under extreme conditions. The dielectric constant ranged from 3 to 9. The excellent electronic quality of aluminum oxide may be attractive for field effect transistor applications.
TL;DR: In this article, the authors review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics, and discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance.
Abstract: The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 mm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown, Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.