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Author

A.N. Karanicolas

Bio: A.N. Karanicolas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Operational amplifier & Fully differential amplifier. The author has an hindex of 5, co-authored 5 publications receiving 569 citations.

Papers
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Journal ArticleDOI
01 Dec 1993
TL;DR: In this paper, a 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented with a radix 1.93, 1 b per stage design, which accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain and capacitor nonlinearity contributing to DNL.
Abstract: A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >

441 citations

Patent
24 Feb 1994
TL;DR: In this paper, a self-calibrating pipeline analog-to-digital converter with a recursive calibrating section is defined, which includes circuitry for receiving an analog output signal generated from the first conversion unit in response to an analog input signal provided to the first converter unit.
Abstract: A self-calibrating pipeline analog-to-digital converter having a plurality of analog-to-digital conversion units and including a recursive calibrating section operable for calibrating errors associated with an immediately preceding first conversion unit. The recursive calibrating section includes circuitry for receiving an analog output signal generated from said first conversion unit in response to an analog input signal provided to the first conversion unit; circuitry for receiving a digital output signal generated from the first conversion unit in response to a digital input signal provided to the first conversion unit; circuitry for generating a conversion signal corresponding to a quantized representation of the analog output signal; and circuitry for generating a calibration signal having a value equal to the conversion signal in response to the digital input signal being a first digital value and having a value equal to the sum of the conversion signal and a calibration value in response to the digital input signal being a second digital value.

72 citations

Journal ArticleDOI
TL;DR: In this article, a high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented, which offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45 degrees phase margin, and a slew rate of 150 V/ mu s.
Abstract: A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2- mu m BiCMOS process with an active die area of 1.0 mm*1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45 degrees phase margin, and a slew rate of 150 V/ mu s. The differential output range is 12 V. The circuit is operated from a +or-5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages. >

35 citations

Journal ArticleDOI
TL;DR: In this paper, the authors describe a one-sided etch method for silicon wafers, which can protect the front side of the substrate to a high degree from the etchant.
Abstract: Silicon micromachining often requires the selective removal of either surface or bulk layers of material from substrates. Often it is advantageous to protect one side of a substrate while the other side is exposed to the etchant. Sometimes an etch can take as long as 8–10 h at temperatures as high as 80 °C, such as in wet etching of bulk silicon in potassium hydroxide (KOH) solution. Other times, the etch may be at room temperature, and there may be prolonged periods of exposure to concentrated hydrofluoric acid (HF) when removing sacrifical layers of oxide. Both KOH and concentrated HF are effective in etching silicon and silicon dioxide respectively, but there is difficulty in finding suitable materials that mask these etchants for long periods of time. Silicon nitride is a good mask for KOH, but is deposited at a relatively high temperature (800 °C), while concentrated HF tends to delaminate or etch most materials. This makes it difficult to protect layers on silicon wafers after any metal deposition. This paper describes a system designed to wet etch substrates from one side only, protecting the front side to a high degree. The one-sided etching concept is introduced, followed by the design of the apparatus with variations on the basic concept. This is followed by a particular implementation in a KOH etching system. Also described as part of the KOH etching system is a simple and economical method for solution level detection based on the conductance of the solution. This detection system compensates for loss of water in the solution due to evaporation when etching at high temperatures. Finally, an example of the usefulness of the one-sided apparatus is given.

20 citations

Proceedings ArticleDOI
13 May 1990
TL;DR: In this paper, a BiCMOS differential operational amplifier designed for use in switched-capacitor circuits is presented, which offers an infinite input resistance, a DC gain of 100 dB, a unity gain frequency of 90 MHz with 45 degrees phase margin, and a slew rate of 150 V/ mu s. The op-amp is operated from a + or 5V power supply and dissipates 125 mW.
Abstract: A BiCMOS differential operational amplifier designed for use in switched-capacitor circuits is presented. This BiCMOS op-amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45 degrees phase margin, and a slew rate of 150 V/ mu s. The op-amp is unity gain stable with 7 pF of capacitive loading. The circuit is operated from a +or-5-V power supply and dissipates 125 mW. The op-amp is integrated in the 3.0-GHz, 2-RGmm MIT BiCMOS process with an active die area of 1.0 mm*1.2 mm. >

10 citations


Cited by
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Journal ArticleDOI
09 Feb 2003
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Abstract: Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.

555 citations

Journal ArticleDOI
01 Dec 1993
TL;DR: In this paper, a 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented with a radix 1.93, 1 b per stage design, which accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain and capacitor nonlinearity contributing to DNL.
Abstract: A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >

441 citations

Proceedings Article
01 Jan 2006
TL;DR: An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion which allows its use in RF subsampling applications.
Abstract: An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth ( 4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous pro- cessing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-in- terleaving two single ADCs, which were fabricated in a 0.13- m standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12 mm and having power consumption of 5.3 mW. Index Terms—Analog-to-digital conversion, analog integrated circuits, asynchronous logic circuits, calibration, capacitive ladder, comparators, high-speed integrated circuits, impulse radio, non- binary successive approximation, ultra-wideband (UWB).

335 citations

Book
31 Jan 2000
TL;DR: The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects and explains in detail how to derive data converter requirements for a given communication system.
Abstract: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

325 citations

Journal ArticleDOI
TL;DR: An asynchronous analog-to-digital converter based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion which allows its use in RF subsampling applications.
Abstract: An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-interleaving two single ADCs, which were fabricated in a 0.13-mum standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12mm2 and having power consumption of 5.3 mW

287 citations