Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient two-step genetic algorithm that has been used to build a tool for mapping an application, described by a parameterized task graph, on to a NoC architecture with a two dimensional mesh of switches as a communication backbone. The computational resources in NoC consist of a set of heterogeneous IP cores. Our algorithm finds a mapping of the vertices of the task graph to available cores so that the overall execution time of the task graph is minimized. We have developed a NoC architecture specific communication delay model to estimate the execution time. Our algorithm is able to handle large task graphs and provide near optimal mapping in a few minutes on a PC platform. Our tool also provides facilities for specifying NoC architecture, generation and viewing synthetic task graphs and viewing the progress of the genetic algorithm as it converges to a solution.

A two-step genetic algorithm for mapping task graphs to a network on chip architecture

Power limitations and complexity constraints demand modular designs, such as chip multiprocessors (CMPs) and systems-on-chip (SOCs). Today's CMPs feature up to a hundred discrete cores, with greater levels of integration anticipated in the future. Supporting effective on-chip resource sharing for cloud computing and server consolidation necessitates CMP-level quality-of-service (QOS) for performance isolation, service guarantees, and security. This work takes a topology-aware approach to on-chip QOS. We propose to segregate shared resources into dedicated, QOS-enabled regions of the chip. We than eliminate QOS-related hardware and its associated overheads from the rest of the die via a combination of topology and operating system support. We evaluate several topologies for the QOS-enabled regions, including a new organization called Destination Partitioned Subnets (DPS) which uses a light-weight dedicated network for each destination node. DPS matches or bests other topologies with comparable bisection bandwidth in performance, area- and energy-efficiency, fairness, and preemption resilience.

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Topology-Aware quality-of-service support in highly integrated chip multiprocessors

This paper describes xENoC, an automatic and component re-use HW-SW environment to build simulatable and synthesizable Network-on-Chip-based MPSoC architectures. xENoC is based on a tool, named NoCWizard, which uses an eXtensible Markup Language (XML) specification, and a set of modularized components and templates to generate many types of NoC instances by using Verilog HDL. This NoC models can be customized in terms of topology, tile location/mapping, RNIs generation, different types of routers, FIFO and packet/flit sizes, by simply modifying the XML specifications. Furthermore, xENoC is also composed of software components, i.e. RNI drivers and a parallel programming model, embedded Message Passing Interface (eMPI), which let us to carry out a complete HW-SW co-design methodology to design distributed-memory NoC-based MPSoCs parallel applications. Through xENoC different distributed-memory NoC-based MPSoCs designs have been created simulated and prototyped in physical platforms (e.g. FPGA boards), and some parallel multiprocessor test traffic applications are running there as system level demonstrators.

xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures

We present a network-on-chip (NoC) architecture that is based on code division multiple access (CDMA) techniques The orthogonality properties of a Walsh code are used to route data packets between resources A star network topology allows a hierarchical switching platform to be constructed which can be scaled to handle large systems The switching element and network topology are described and algorithms for modulation and demodulation of packets are presented Simulation results for throughput and latency are given

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CDMA-based network-on-chip architecture

Network on Chip (NoC) is a new paradigm for designing core based System on Chip. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Genetic Algorithm and the correlated software will be described mapping concurrent applications, which are described by parameterized multi-task-graph, onto a NoC with two dimensional mesh of switches as a communication backbone and populated with a known set of IP cores as computational resources. The algorithm proposes mathematical delay models and finds a good method of mapping vertices of the multi-task-graph to available cores so that every single task graph can meet its respective deadline. The correlated software has two separate tools. One can freely generate any NoC backbone and multi-task-graph for test. The other achieves Two-Step Genetic Algorithm and can give the design result within one minute on a PC platform. It also provides facilities for viewing synthetic task graphs and the working progress of genetic algorithm.

Algorithms and tools for network on chip based system design

Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOC-based systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.

A. Pelkonen

Papers

Extending platform-based design to network on chip systems