A. Tanabe

Bio: A. Tanabe is an academic researcher from NEC. The author has contributed to research in topics: RF probe & Capacitance. The author has an hindex of 1, co-authored 1 publications receiving 5 citations.

A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model

Abstract: RF characteristics for sub-0.1μm MOSFETs such as fT, fmax and their variations are estimated from the DC and capacitance parameters. A new RF gate resistance model with a silicide-polysilicon interface resistance is a key factor to estimate the RF characteristics precisely. The variations of RF characteristics are also inferred from correlation coefficient between the RF parameters and the DC and capacitance parameters. This method is effective in monitoring RF characteristics and their variations for scaled-down, RF/mixed-signal circuits at the chip fabrication.

Investigation of Parasitic Effects and Design Optimization in Silicon Nanowire MOSFETs for RF Applications

Abstract: The design of silicon nanowire MOSFETs (SNWTs) for RF applications is discussed in this paper based on 3-D simulation, including the impacts of the parasitic capacitances and resistance. The results indicate that large parasitic capacitances are a dominant factor for nanowire structure, which can significantly degrade the ac characteristics of SNWTs. Resistance of the ultranarrow source/drain extension (SDE) regions, which is the main contributor to the total series resistance of SNWTs, is another important factor influencing the device performance. The requirement of contact resistance of source/drain regions in SNWTs is relatively relaxed compared to the SDE regions. Considering the tradeoff between parasitic capacitances and resistance, optimization of the doping profile in SDE regions of SNWTs with 10-nm gate length is further investigated for RF applications.

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

Abstract: The fluctuation of RF performance (particularly for fT: cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for fT fluctuation is well fitted with the measurement data within approximately 1% error. Low-Vt transistors (fabricated by lower doping concentration in the channel) show higher fT fluctuation than normal transistors. Such a higher fT fluctuation results from Cgg (total gate capacitance) variation rather than gm variation. More detailed analysis shows that Cgs + Cgb (charges in the channel and the bulk) are predominant factors over Cgd (charges in LDD/halo region) to determine Cgg fluctuation.

Modeling gate resistance of a multi-fin multi-gate field effect transistor

Abstract: The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element.

A novel small capacitance RF-MOSFET with small-resistance Long-finger Gate Electrode

Abstract: We have developed a small capacitance RF-MOSFET with small-resistance long-finger gate electrode, which is featured by Direct Finger Contact (DFC) on the gate electrode in active region to reduce its resistance. The unique structure and layout, which is different from a conventional multiplied-short-finger MOSFET, suppress the parasitic capacitance around the gate electrode to obtain high f T . This layout-optimized DFC MOSFET is very useful for RF/Mixed signal SoCs in deep-sub-micron generations.

45nm PD SOI FET gate resistance optimization for mmw applications

Abstract: This paper investigates the impact of phosphorous polysilicon gate pre-doping and silicide thickness on the gate resistance of NFETs. The analysis is performed on a 45nm partially depleted (PD) Silicon-on-Insulator (SOI) technology with a Ni silicided poly SiON gate stack. It is shown that both process features contribute differently to R g improvements, making their respective benefits dependent on device finger width (W f ). The data also show that combining both approaches can simultaneously improve R g and, consequently, device maximum oscillation frequency (F max ) on both small and large W f devices.