A. Tawfik

Bio: A. Tawfik is an academic researcher from Ajman University of Science and Technology. The author has contributed to research in topics: Digital watermarking & Digital filter. The author has an hindex of 9, co-authored 46 publications receiving 234 citations. Previous affiliations of A. Tawfik include Ain Shams University & Victoria University, Australia.

A novel blind image watermarking technique for colour RGB images in the DCT domain using green channel

Abstract: This paper presents a new algorithm for colour digital image watermarking. The 24 bits/pixel RGB images are used and the watermark is placed on the green channel of the RGB image. The green channel is chosen after an analytical investigation process was carried out using some popular measurement metrics. The analysis and embedding processes have been carried out using the discrete cosine transform DCT. The new watermarking method has shown to be resistant to JPEG compression, cropping, scaling, low-pass, median and removal attack. This algorithm produces more than 65 dB of average PSNR.

Watermarking of colour images in the DCT domain using Y channel

Abstract: In this paper an image authentication technique that embeds a binary watermark into a host color image is proposed. In this scheme the colour image is first transformed from the RGB to the YCbCr color space. The watermark is embedded into the Y channel of the host image by selectively modifying the very low frequency parts of the DCT transformation. It is shown that the proposed technique can resist classical attacks such as JPEG Compression, low pass filtering, median filtering, cropping, and geometrical scaling attack. Moreover, the recovery method is blind and doesn't need the original host image for extraction.

Mapping 3-D IIR digital filter onto systolic arrays

Abstract: We present here an efficient systolic implementation for 3-D IIR digital filters. The systolic implementation is obtained by using an algebraic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variables propagations and the data feeding and extracting points. The resultant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic implementation is regular, modular and amenable to VLSI Implementation.

A New Watermarking Scheme For Colour Images Captured By Mobile Phone Cameras

Abstract: Summary A new frequency domain based watermarking scheme for colour images captured by mobile phone cameras is proposed. The proposed technique embeds personal mobile phone numbers inside the image. The aim of the scheme is to protect the copy right ownership of the image. Each bit of the decimal digits is inserted onto one low frequency coefficient of one of the DCT blocks of the host image. A DCT coefficient selection (DCS) process has been applied to increase the invisibility qualities, this process managed to find the coefficient with the maximum magnitude. Different embedding location depending on the spatial frequencies of the host image will be selected. The proposed algorithm achieves a high PSNR values and is found to be robust against JPEG compression and different image manipulation algorithms.

A New Blind Image Watermarking of Handwritten Signatures using Low-Frequency Band DCT Coefficients

Abstract: This paper deals with a new blind technique for robust image watermarking in the DCT domain. The technique is based on embedding watermark information in eight low-frequency band coefficients of the DCT sub-blocks. Single watermark has been embedded multi-times in the host image. The embedding process is based on changing the selected DCT-coefficients of the host image to odd or even values depending on the binary watermark's bit value. The proposed blind watermarking embedding has shown to be strongly robust against several attacks.

Integer wavelet transform for embedded lossy to lossless image compression

Abstract: The use of the discrete wavelet transform (DWT) for embedded lossy image compression is now well established. One of the possible implementations of the DWT is the lifting scheme (LS). Because perfect reconstruction is granted by the structure of the LS, nonlinear transforms can be used, allowing efficient lossless compression as well. The integer wavelet transform (IWT) is one of them. This is an interesting alternative to the DWT because its rate-distortion performance is similar and the differences can be predicted. This topic is investigated in a theoretical framework. A model of the degradations caused by the use of the IWT instead of the DWT for lossy compression is presented. The rounding operations are modeled as additive noise. The noise are then propagated through the LS structure to measure their impact on the reconstructed pixels. This methodology is verified using simulations with random noise as input. It predicts accurately the results obtained using images compressed by the well-known EZW algorithm. Experiment are also performed to measure the difference in terms of bit rate and visual quality. This allows to a better understanding of the impact of the IWT when applied to lossy image compression.

A fast parallel multiplier-accumulator using the modified Booth algorithm

Abstract: This paper presents a dependence graph (DG) to visualize and describe a merged multiply-accumulate (MAC) hardware that is based on the modified Booth algorithm (MBA). The carry-save technique is used in the Booth encoder, the Booth multiplier, and the accumulator sections to ensure the fastest possible implementation. The DG applies to any MAC data word size and allows designing multiplier structures that are regular and have minimal delay, sign-bit extensions, and datapath width. Using the DG, a fast pipelined implementation is proposed, in which an accurate delay model for deep submicron CMOS technology is used. The delay model describes multi-level gate delays, taking into account input ramp and output loading. Based on the delay model, the proposed pipelined parallel MAC design is three times faster than other parallel MAC schemes that are based on the MBA. The speedup resulted from merging the accumulate and the multiply operations and the wide use of carry-save techniques.

A Video Watermarking Technique Based on Pseudo-3-D DCT and Quantization Index Modulation

Abstract: The increasing popularity of the internet means that digital multimedia are transmitted more rapidly and easily. And people are very aware for media ownership. However, digital watermarking is an efficient and promising means to protect intellectual properties. Based on the intellectual property attention in the information era, how to protect the personal ownership is extremely important and a necessary scheme. In this paper, we propose an effective video watermarking method based on a pseudo-3-D discrete cosine transform (DCT) and quantization index modulation (QIM) against several attacks. The watermark is mainly inserted into the uncompressed domain by adjusting the correlation between DCT coefficients of the selected blocks, and the watermark extraction is blind. This approach consists of a pseudo-3-D DCT, watermark embedding, and extraction. A pseudo-3-D DCT, which is taken DCT transformation twice, will be first utilized to calculate the embedding factor and to obtain the useful messages. Using the QIM, we embed the watermark into the quantization regions from the successive raw frames in the uncompressed domain and record the relative information to create a secret embedding key. This secret embedding key will further apply to extraction. Experimental results demonstrate that the proposed method can survive filtering, compressions, luminance change, and noise attacks with a good invisibility and robustness.

New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm

Abstract: In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.