A. Van den Bosch

Bio: A. Van den Bosch is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Computer science. The author has an hindex of 13, co-authored 22 publications receiving 1104 citations.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Abstract: In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters

Abstract: Although very high update rates are achieved in recent publications on high resolution D/A converters, the bottleneck in the design is to achieve a high spurious free output signal bandwidth. The influence of the dynamic output impedance on the chip performance has been analyzed and has been identified as an important limitation for the spurious free dynamic range (SFDR) of high resolution DAC's. Based on the presented analysis an optimized topology is proposed.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Abstract: In this paper, a 10 bit 1 GS/s current-steering CMOS D/A converter is presented. The measured INL is better than +/-0.2 LSB. The 1 GS/s conversion rate has been obtained by a fully custom designed thermometer decoder. The dynamic limitations have been solved, resulting in more than 61 dB measured SFDR in the interval from DC to Nyquist at all conversion rates up to 1 GS/s. At this conversion rate, the power consumption equals 110 mW. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

Randomized clinical trial of laparoscopic colectomy with or without natural-orifice specimen extraction

Abstract: Background Although conventional laparoscopic colectomy is a validated technique, laparoscopic natural-orifice specimen extraction (NOSE) colectomy might improve outcome. This randomized clinical trial compared analgesia requirements, postoperative pain, anorectal function, inflammatory response and cosmesis in laparoscopic NOSE colectomy and conventional laparoscopic colectomy. Methods Patients were randomly assigned to undergo laparoscopic NOSE colectomy or conventional laparoscopic colectomy for left-sided colonic disease. The primary endpoint was analgesia requirement. Secondary endpoints were operative outcome, inflammatory response, anorectal function and cosmesis. Results Forty patients were enrolled in the study, 20 in each group (15 with diverticulitis and 5 with colorectal cancer in each group). A significant difference was observed in morphine analogue requirements (1 of 20 patients in the NOSE group versus 10 of 20 in the conventional group; P = 0·003). Patient-controlled epidural analgesia was lower in the NOSE group (mean 116 ml versus 221 ml in the conventional group; P < 0·001), as was paracetamol use (mean 11·0 versus 17·0 g respectively; P < 0·001). Postoperative pain scores were lower in the NOSE group: mean maximum visual analogue score of 3·5 versus 2·1 (P < 0·001). One week after hospital discharge, pain scores remained higher in the conventional group: 15 of 20 patients in the conventional group reported pain, compared with one of 20 in the NOSE group (P < 0·001). Inflammatory responses were greater in patients undergoing NOSE colectomy: higher peak C-reactive protein and interleukin 6 levels were observed on postoperative day 2 (P < 0·001) and day 1 (P = 0·002) respectively. Postoperative anorectal function, complications and hospital stay were similar in the two groups. Conclusion Laparoscopic NOSE colectomy was associated with less pain and lower analgesia requirements than the conventional laparoscopic extraction. Registration number: NCT01033838 (http://www.clinicaltrials.gov).

An accurate statistical yield model for CMOS current-steering D/A converters

Abstract: To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

FinFETs and Other Multi-Gate Transistors

Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

Device mismatch and tradeoffs in the design of analog circuits

Abstract: Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Abstract: In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

CMOS Data Converters for Communications

Abstract: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

Abstract: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply