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A. Vasilopoulos

Bio: A. Vasilopoulos is an academic researcher from National and Kapodistrian University of Athens. The author has contributed to research in topics: CMOS & Noise figure. The author has an hindex of 3, co-authored 6 publications receiving 133 citations.

Papers
More filters
Journal ArticleDOI
TL;DR: A low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth and a digital automatic tuning scheme to account for process and temperature variations is presented.
Abstract: In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12-mum CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately +20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively

126 citations

Journal ArticleDOI
TL;DR: A CMOS low-noise amplifier that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance is presented.
Abstract: A CMOS low-noise amplifier that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance is presented. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB, and best-case third-order input intercept point of 13 dBm. The design is being implemented in a 0.13-mum CMOS technology

6 citations

Proceedings ArticleDOI
21 May 2006
TL;DR: A software tool that facilitates a fast optimization of the mixer's linearity performance has been developed and results confirm excellent match with those obtained by popular commercial SPICE-like simulators, whereas simulation time is lowered by an order of magnitude.
Abstract: In this paper, an intermodulation distortion analysis for active CMOS mixers based on Volterra series theory is presented. As an outcome of the analysis, a software tool that facilitates a fast optimization of the mixer's linearity performance has been developed. Results from the tool confirm excellent match with those obtained by popular commercial SPICE-like simulators, whereas simulation time is lowered by an order of magnitude.

5 citations

Proceedings ArticleDOI
03 Dec 2022
TL;DR: In this paper , a different approach based on directly minimizing the MVM error using gradient descent with synthetic random input data was proposed to improve the performance of unit-cell matrix vector multiplication.
Abstract: The precise programming of crossbar arrays of unit-cells is crucial for obtaining high matrix-vector-multiplication (MVM) accuracy in analog in-memory computing (AIMC) cores. We propose a radically different approach based on directly minimizing the MVM error using gradient descent with synthetic random input data. Our method significantly reduces the MVM error compared with conventional unit-cell by unit-cell iterative programming. It also eliminates the need for high-resolution analog-to-digital converters (ADCs) to read the small unit-cell conductance during programming. Our method improves the experimental inference accuracy of ResNet-9 implemented on two phase-change memory (PCM)-based AIMC cores by 1.26%.

2 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented and a biquad cell with simple architecture is used to reduce power consumption and improve the linearity of the filter.
Abstract: A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture is used. A simple but efficient technique is also proposed to improve the linearity of the filter without increasing its power consumption. Coarse and fine tuning techniques are used to tune the cutoff frequency of the sixth-order Butterworth low-pass filter from 8.1 MHz to 13.5 MHz suitable for WLAN and WiMAX applications. The measurement results show an in-band IIP3 of + 22 dBm, an HD3 better than - 40 dB at 470 mVP input signal amplitude, and an input referred noise of 75 nV/√Hz at a power consumption of 4.35 mW from a 1-V supply. The differential filter occupies a chip area of 0.239 mm2 excluding pads.

98 citations

Journal ArticleDOI
TL;DR: This paper proposes a biquad design methodology and presents a baseband low-pass filter for wireless and wireline applications with reconfigurable frequency response (Chebyshev/Inverse ChebysheV), selectable order, continuously tunable cutoff frequency, and adjustable power consumption.
Abstract: This paper proposes a biquad design methodology and presents a baseband low-pass filter for wireless and wireline applications with reconfigurable frequency response (Chebyshev/Inverse Chebyshev), selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1-20 MHz), and adjustable power consumption (3-7.5 mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel continuous impedance multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and inverse Chebyshev approximation types. Also, a new stability metric for biquads, minimum acceptable phase margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3 dBm, a THD of -40 dB at 447 mVpk, diff input signal amplitude, and a DR of 71.4 dB. The filter's tunable range covers frequencies from 1 MHz to 20 MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than plusmn2.5%. The design is fabricated in 0.13 mum CMOS, occupies 1.53 mm2 , and operates from a 1-V supply.

85 citations

Journal ArticleDOI
TL;DR: In this paper, the effect of noise correlation on eigenvalue-based spectrum sensing (SS) is analyzed under both the noise-only and signal-plus-noise hypotheses.
Abstract: Herein, we present a detailed analysis of an eigenvalue-based sensing technique in the presence of correlated noise in the context of a cognitive radio (CR). We use standard-condition-number (SCN)-based decision statistics based on asymptotic random matrix theory (RMT) for the decision process. First, the effect of noise correlation on eigenvalue-based spectrum sensing (SS) is analytically studied under both the noise-only and signal-plus-noise hypotheses. Second, new bounds for the SCN are proposed to achieve improved sensing in correlated noise scenarios. Third, the performance of fractional-sampling (FS)-based SS is studied, and a method to determine the operating point for the FS rate in terms of sensing performance and complexity is suggested. Finally, a signal-to-noise ratio (SNR) estimation technique based on the maximum eigenvalue of the covariance matrix of the received signal is proposed. It is shown that the proposed SCN-based threshold improves sensing performance in correlated noise scenarios, and SNRs up to 0 dB can be reliably estimated with a normalized mean square error (MSE) of less than 1% in the presence of correlated noise without the knowledge of noise variance.

82 citations

Journal ArticleDOI
Le Ye1, Congyin Shi1, Huailin Liao1, Ru Huang1, Yangyuan Wang1 
TL;DR: A generic-purpose solution of highly power-efficient active-RC filters, suitable for analog baseband with wide bandwidth-range from several mega- Hz to hundreds of mega-Hz in wireless receivers, and the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation.
Abstract: This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 μA 7-20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240-500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 μm CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 μA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/√ Hz IRN density, and occupies 0.21 mm 2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/√ Hz IRN density, and occupies 0.23 mm 2 silicon area without pads.

71 citations

Journal ArticleDOI
TL;DR: A discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation and its sampling rate is then multiplied through pipelining, thus being compatible with digital nanoscale technology.
Abstract: In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/$surd$ Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm 2.

70 citations