This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. In [34], Simpson and Schaumont proposed a fundamentally different approach to IP protection on FPGAs based on the use of Physical Unclonable Functions (PUFs). Their work only assumes the existence of a PUF on the FPGAs without actually proposing a PUF construction. In this paper, we propose new protocols for the IP protection problem on FPGAs and provide the first construction of a PUF intrinsic to current FPGAs based on SRAM memory randomness present on current FPGAs. We analyze SRAM-based PUF statistical properties and investigate the trade offs that can be made when implementing a fuzzy extractor.

/pdf/fpga-intrinsic-pufs-and-their-use-for-ip-protection-4zcbpcd9em.pdf

FPGA Intrinsic PUFs and Their Use for IP Protection

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

/pdf/low-power-logic-styles-cmos-versus-pass-transistor-logic-40lwlx0imm.pdf

Low-power logic styles: CMOS versus pass-transistor logic

This paper describes a complete digital PWM controller IC for high-frequency switching converters. Novel architecture and configurations of the key building blocks are A/D converter, compensator, and digital pulse-width modulator, are introduced to meet the requirements of tight output voltage regulation, high-speed dynamic response, and programmability without external passive components. The implementation techniques are experimentally verified on a prototype chip that takes less than 1 mm/sup 2/ of silicon area in a standard 0.5 /spl mu/ digital complementary metal oxide semiconductor (CMOS) process and operates at the switching frequency of 1 MHz.

/pdf/high-frequency-digital-pwm-controller-ic-for-dc-dc-2vpkurwra9.pdf

High-frequency digital PWM controller IC for DC-DC converters

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V/sub DD/ and V/sub T/ to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-/spl mu/m test chip is used to compare normal sizing and sizing to minimize operational V/sub DD/ and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Modeling and sizing for minimum energy operation in subthreshold circuits

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.

Circuit techniques for CMOS low-power high-performance multipliers

Low-Power Digital VLSI Design

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

Low-power direct digital frequency synthesis for wireless communications

CMOS supply voltage scaling for temperature independent gate delay is investigated. It is found that the optimum supply voltage which results in temperature insensitive operation is proportional to the threshold voltage. This voltage enables a single battery cell operation. CMOS technologies with 0.35- and 0.25-/spl mu/m size features are used as examples in this study.

Supply voltage scaling for temperature insensitive CMOS circuit operation

The key issues in ultralow voltage SRAM design are a reduction in power supply voltage to a solar-cell voltage of 0.5V or less, single supply operation, and an increase in the cell voltage-margin. However, these problems remain largely unsolved. Even in most advanced cells an unavoidably high FET threshold voltage (V/sub T/) of the cell compared with the low stored node-voltage of supply restricts the supply to around 1V, although 0.5 V operation has been reported with no cell margin. Moreover, the negative pull down of the cell source line prevents single supply operation, since an on-chip negative voltage generator comprising charge pumping circuits never manages a heavy data-line capacitance. This paper describes an innovative circuit for overcoming these problems, demonstrating the feasibility of a single 0.3 V, 50 MHz, 0.25 /spl mu/m 8Kb SRAM. A multi-V/sub T/ cell, a boosted cell storage-node and a dynamic cell load contribute to the outstanding performance.

Abdellatif Bellaouar

Papers

Circuit techniques for CMOS low-power high-performance multipliers

Low-Power Digital VLSI Design

Low-power direct digital frequency synthesis for wireless communications

Supply voltage scaling for temperature insensitive CMOS circuit operation

A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load