Abdul Majeed K.K
Bio: Abdul Majeed K.K is an academic researcher. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 6 citations.
01 Dec 2015
TL;DR: Two novel voltage controlled oscillators (CSN-V CO and CSD-VCO) have been proposed in this paper and the step response has been compared with the circuit simulation results from Cadence.
Abstract: Two novel voltage controlled oscillators (CSN-VCO and CSD-VCO) have been proposed in this paper. CSN-VCO has been designed with 20 transistors while CSD VCO with 24 transistors. It has been observed that CSN-VCO could operate in the frequency range from 0.066 to 2.2 GHz, and CSD VCO could operate from 0.047 to 2.5 GHz. Tuning range for these VCOs are determined to be 97 %, and 98.2 % while the values of gain obtained are 8.94 and 10.2 GradV−1 respectively. Phase noise analysis has been performed and the phase noise contribution by CSN-VCO and CSD VCO are found to be −126 and −129 dBc/Hz @ 1 MHz respectively. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK090 library of 180 nm technology with a supply voltage of 1.8 V. Simulation of transfer function of PLL built with the VCOs has been done in MATLAB and the step response has been compared with the circuit simulation results from Cadence. Lock time as low as 355 ns and 313 ns have been achieved for the CSN-VCO and CSD-VCO respectively.
TL;DR: In this paper, a phase-locked loop (PLL) was designed using a linear PFD which is free of dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO.
Abstract: This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.
TL;DR: A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study.
Abstract: A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δφ > π and provides a lower-gain and loop BW during tracking when Δφ <; π as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal-oxide-semiconductor process is found to achieve reference spur of -71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of -110 dBc/Hz at 100 kHz and final placement area of 0.244 mm 2 .
TL;DR: In this paper, a phase lock loop (PLL) performance was optimized subject to the practical design constraints using an efficient multi-objective optimization technique, infeasibility driven evolutionary algorithm (IDEA), in a real-time environment using design parameters like the channel length and width of the MOSFETs for optimal performance.
Abstract: CMOS integrated circuits consisting of MOSFETs have tradeoffs among their performance parameters Hence they need minimization in those tradeoffs calling for multi objective optimization to yield a circuit with enhanced characteristics To perform simultaneous optimization of the Phase locked loop (PLL) performances using an effective multi objective optimization technique saving the designer’s time and causing the near best performance is the motivation of this work Though the designer can optimize the circuit in the netlist level, it is less effective and a time consuming iterative process and sometimes it is next to impossible for complex and nanoscale circuits with large number of MOSFET devices and interconnects Performance parameters like phase noise, lock time and power consumption are optimized subject to the practical design constraints using an efficient multi-objective optimization technique, infeasibility driven evolutionary algorithm (IDEA) in a real time environment Using design parameters like the channel length and width of the MOSFETs for optimal performance, the PLL is simulated for model validation Significantly superior performance achieved by the designed PLL is demonstrated The phase noise, average power consumption and lock time achieved here are −1263 dBc/Hz at 1 MHz offset frequency, 1523 mW and 50 nS respectively
••01 Jul 2018
Abstract: A tri-state charge pump circuit and second order low pass filter circuit were designed to be used in Phase Lock Loop (PLL) system. The proposed design reduces the non-ideal effects such as a current mismatch and charge sharing. Therefore, it can be minimized by providing an equal value for the two switches UP and DOWN. While the charge pump output determines the output condition of the low pass filter. The proposed design have been simulated by using 130nm Complementary Metal Oxide Semiconductor (CMOS) technology in Cadence Tools. The simulation also includes the parameters for tri-state charge pump and second order low pass filter using voltage supply of 1.2 V. The power consumption of the design is 2.07 mW with the output voltage swing from 288 mV to 413.8 mV. The frequency achieved from the proposed design is 4.7 GHz. The total area of the layout that have been measured is 31.4 µm x 22.6 µm (0.7096 mm2). Thus, the proposed design able to achieve the scope of low power consumption and high frequency in smaller technology.
••11 Feb 2021
TL;DR: In this paper, a transmission gate phase frequency detector (TG-PFD) was designed and implemented for fast locking and low Reference Spur PLL working in Giga-Hertz choice.
Abstract: This work has been paying attention to design and implement a Transmission gate phase frequency detector (TG-PFD) for Fast locking and low Reference Spur PLL working in Giga-Hertz choice. It has been experiential that the projected TG-PFD could completely erase delay for reset thereby eliminating dead region and blind region as well. By inclusion of the transmission gate into the PFD, could enhance the magnitude of the output signal and hence could improve the loop band and obtained a PLL with reduced locking time. Leakage current minimized as a result of adding CMOS inverters at the output of the TG-PFD and thereby obtained better reference spur for the Phase Locked Loop implemented using TG-PFD. Reference Spur of −77.2 dBc, locking time of 2.83 µs have been obtained for the designed PLL using projected TG-PFD in 180 nm CMOS technology which is exactly matching with the mathematical analysis done by this paper.