Abdulqader Mahmoud

Bio: Abdulqader Mahmoud is an academic researcher from Delft University of Technology. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 7, co-authored 26 publications receiving 212 citations. Previous affiliations of Abdulqader Mahmoud include Khalifa University.

Introduction to spin wave computing

Abstract: This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages. Spin-wave computing can be considered a subfield of spintronics, which uses magnetic excitations for computation and memory applications. The Tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field toward practical spin-wave circuits. After an introduction to magnetic interactions and spin-wave physics, the basic aspects of spin-wave computing and individual spin-wave devices are reviewed. The focus is on spin-wave majority gates as they are the most prominently pursued device concept. Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input–output consistency, and fan-out achievement. We argue that spin-wave circuits need to be embedded in conventional complementary metal–oxide–semiconductor (CMOS) circuits to obtain complete functional hybrid computing systems. The state of the art of benchmarking such hybrid spin-wave–CMOS systems is reviewed, and the current challenges to realize such systems are discussed. The benchmark indicates that hybrid spin-wave–CMOS systems promise ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of the power-delay-area product. Current challenges to achieve this goal include low-power signal restoration in spin-wave circuits as well as efficient spin-wave transducers.

An Introduction to Spin Wave Computing

Abstract: This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages Spin-wave computing can be considered as a subfield of spintronics, which uses magnetic excitations for computation and memory applications The tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field towards practical spin-wave circuits After an introduction to magnetic interactions and spin-wave physics, all relevant basic aspects of spin-wave computing and individual spin-wave devices are reviewed The focus is on spin-wave majority gates as they are the most prominently pursued device concept Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input-output consistency, and fan-out achievement We argue that spin-wave circuits need to be embedded in conventional CMOS circuits to obtain complete functional hybrid computing systems The state of the art of benchmarking such hybrid spin-wave--CMOS systems is reviewed and the current challenges to realize such systems are discussed The benchmark indicates that hybrid spin-wave--CMOS systems promise ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of the power-delay-area product Current challenges to achieve this goal include low-power signal restoration in spin-wave circuits as well as efficient spin-wave transducers

Fan-out enabled spin wave majority gate

Abstract: By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fanout capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fanout of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible, proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15 nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires a 12× less area than the 15 nm CMOS MAJ3 gate and that at the gate level, the fanout capability results in 16% area savings, when compared to the state-of-the-art SW majority gate counterparts.

A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications

Abstract: This paper presents a single-stage power management unit to boost and regulate a low supply voltage for CMOS system-on-chip (SoC) applications. It consists of low-leakage, enhanced Dickson charge pump (DCP) that utilizes both stage and frequency modulation (FM) techniques to achieve high efficiency and lower area. In addition, the proposed design uses an enhanced stage-switch structure for the charge pump, which significantly reduces the cross-stage leakage. A stage number controller is used to control the gain of the charge pump by changing the number of stages based on the desired output voltage. FM is utilized to further fine-tune the output voltage through a closed-loop control based on a predetermined reference voltage. Silicon measurement results for the four-stage charge pump in 65-nm CMOS technology show a maximum end-to-end efficiency of 66% at an input voltage of 0.7 V and an output power of $27~\mu \text{W}$ . The proposed design achieved more than a $100\times $ reduction in leakage compared to traditional DCP. The system supports a range of load currents between 0.1 and $34~\mu \text{A}$ with a maximum operating frequency of 1.8 MHz. The proposed system supports an input voltage range of 0.55–0.7 V which makes it an excellent candidate for solar and thermal energy-harvesting applications targeting low-power internet-of-things SOC.

Spin Wave Normalization Towards all Magnonic Circuits

Abstract: The key enabling factor for Spin Wave (SW) technology utilization for building ultra low power circuits is the ability to energy efficiently cascade SW basic computation blocks. SW Majority gates, which constitute a universal gate set for this paradigm, operating on phase encoded data are not input output coherent in terms of SW amplitude, and as such, their cascading requires information representation conversion from SW to voltage and back, which is by no means energy effective. In this paper, a novel conversion free SW gate cascading scheme is proposed that achieves SW amplitude normalization by means of a directional coupler. After introducing the normalization concept, we utilize it in the implementation of three simple circuits and, to demonstrate its bigger scale potential, of a 2-bit inputs SW multiplier. The proposed structures are validated by means of the Object Oriented Micromagnetic Framework (OOMMF) and GPU-accelerated Micromagnetics (MuMax3). Furthermore, we assess the normalization induced energy overhead and demonstrate that the proposed approach consumes 20% to 33% less energy when compared with the transducers based conventional counterpart. Finally, we introduce a normalization based SW 2-bit inputs multiplier design and compare it with functionally equivalent SW transducer based and 16nm CMOS designs. Our evaluation indicate that the proposed approach provided 26% and 6.25x energy reductions when compared with the conventional approach and 16nm CMOS counterpart, respectively, which demonstrates that our proposal is energy effective and opens the road towards the full utilization of the SW paradigm potential and the development of SW only circuits.

Electrical switching of an antiferromagnet

Abstract: Manipulating a stubborn magnet Spintronics is an alternative to conventional electronics, based on using the electron's spin rather than its charge. Spintronic devices, such as magnetic memory, have traditionally used ferromagnetic materials to encode the 1's and 0's of the binary code. A weakness of this approach—that strong magnetic fields can erase the encoded information—could be avoided by using antiferromagnets instead of ferromagnets. But manipulating the magnetic ordering of antiferromagnets is tricky. Now, Wadley et al. have found a way (see the Perspective by Marrows). Running currents along specific directions in the thin films of the antiferromagnetic compound CuMnAs reoriented the magnetic domains in the material. Science, this issue p. 587; see also p. 558 Transport and optical measurements are used to demonstrate the switching of domains in the antiferromagnetic compound CuMnAs. [Also see Perspective by Marrows] Antiferromagnets are hard to control by external magnetic fields because of the alternating directions of magnetic moments on individual atoms and the resulting zero net magnetization. However, relativistic quantum mechanics allows for generating current-induced internal fields whose sign alternates with the periodicity of the antiferromagnetic lattice. Using these fields, which couple strongly to the antiferromagnetic order, we demonstrate room-temperature electrical switching between stable configurations in antiferromagnetic CuMnAs thin-film devices by applied current with magnitudes of order 106 ampere per square centimeter. Electrical writing is combined in our solid-state memory with electrical readout and the stored magnetic state is insensitive to and produces no external magnetic field perturbations, which illustrates the unique merits of antiferromagnets for spintronics.

The 2016 terahertz science and technology roadmap

Abstract: Science and technologies based on terahertz frequency electromagnetic radiation (100 GHz–30 THz) have developed rapidly over the last 30 years. For most of the 20th Century, terahertz radiation, then referred to as sub-millimeter wave or far-infrared radiation, was mainly utilized by astronomers and some spectroscopists. Following the development of laser based terahertz time-domain spectroscopy in the 1980s and 1990s the field of THz science and technology expanded rapidly, to the extent that it now touches many areas from fundamental science to 'real world' applications. For example THz radiation is being used to optimize materials for new solar cells, and may also be a key technology for the next generation of airport security scanners. While the field was emerging it was possible to keep track of all new developments, however now the field has grown so much that it is increasingly difficult to follow the diverse range of new discoveries and applications that are appearing. At this point in time, when the field of THz science and technology is moving from an emerging to a more established and interdisciplinary field, it is apt to present a roadmap to help identify the breadth and future directions of the field. The aim of this roadmap is to present a snapshot of the present state of THz science and technology in 2017, and provide an opinion on the challenges and opportunities that the future holds. To be able to achieve this aim, we have invited a group of international experts to write 18 sections that cover most of the key areas of THz science and technology. We hope that The 2017 Roadmap on THz science and technology will prove to be a useful resource by providing a wide ranging introduction to the capabilities of THz radiation for those outside or just entering the field as well as providing perspective and breadth for those who are well established. We also feel that this review should serve as a useful guide for government and funding agencies.

Ferromagnetic resonance linewidth in metallic thin films: Comparison of measurement methods | NIST

Abstract: Stripline (SL), vector network analyzer (VNA), and pulsed inductive microwave magnetometer (PIMM) techniques were used to measure the ferromagnetic resonance (FMR) linewidth for a series of Permalloy films with thicknesses of 50 and 100nm. The SL-FMR measurements were made for fixed frequencies from 1.5to5.5GHz. The VNA-FMR and PIMM measurements were made for fixed in-plane fields from 1.6to8kA∕m (20–100Oe). The results provide a confirmation, lacking until now, that the linewidths measured by these three methods are consistent and compatible. In the field format, the linewidths are a linear function of frequency, with a slope that corresponds to a nominal Landau-Lifshitz phenomenological damping parameter α value of 0.007 and zero frequency intercepts in the 160–320A∕m (2–4Oe) range. In the frequency format, the corresponding linewidth versus frequency response shows a weak upward curvature at the lowest measurement frequencies and a leveling off at high frequencies.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

Cascaded Logic Gates in Nanophotonic Plasmon Networks

Abstract: Modern electronics based on semiconductors is meeting the fundamental speed limit caused by the interconnect delay and large heat generation when the sizes of components reach nanometer scale. Photons as a carrier of the information are superior to electrons in bandwidth, density, speed, and dissipation. More over, photons could carry intensity, polarization, phase, and frequency information which could break through the limitation of binary system as in electronic devices. But due to the diffraction limitation, the photonic components and devices can not be fabricated small enough to be integrated densely. Surface plasmon polariton is quanta of collective oscillations of free electrons excited by photons in metal nanostrucrures, which offers a promising way to manipulate light at the nanoscale and to realize the miniaturization of photonic devices. Hence, plasmonic circuits and devices have been proposed for some time as a potential strategy for advancing semiconductor-based computing beyond the fundamental performance limitations of electronic devices, as epitomized by Moore's law. A variety of individual plasmonic nanodevices have been intensively studied recently, but the crucial and necessary step to enable nanophotonic circuits for future information technology, namely cascade logics integrated on-chip, has not been achieved. Here we demonstrate that a nanophotonic binary logic NOR gate can be realized by cascading plasmonic OR and NOT gates in four-terminal nanowire networks. We explain the operating principle for the device based on quantum dot luminescence imaging, which reveal the interferences for different logic functions between propagating plasmon wave packets in the nanowire network in great detail. Since the NOR gate is logic complete, i.e. any Boolean logic gate can be constructed from it, our results could have a key role in defining a viable path for the development of novel subwavelength optical processor architectures.