Abhijit Biswas

Abstract: Two-dimensional (2D) analytical models for the threshold voltage and subthreshold slope of fully depleted symmetric double gate (DG) n-MOSFETs have been presented in this paper. 2D Poisson's equation has been solved with suitable boundary conditions to obtain the surface potential at the Si/SiO2 interface. The minimum surface potential has been employed to derive analytical expressions for the threshold voltage and subthreshold slope. Also, these expressions have been modified taking into account the effect of bandgap narrowing due to heavy channel doping and quantum-mechanical effects. In addition, the 2D numerical simulation results obtained using the device simulator ATLAS for the surface potential, the threshold voltage and subthreshold slope have been presented. Further our analytical data have been compared with numerical simulation results for various DG MOSFETs, and our analytical simulation results have also been compared with reported experimental data in the literature. A good agreement is observed among the three, ensuring the validity of our present model. The proposed model is simple and makes it easy to understand the influence of physical phenomena such as quantum-mechanical effects on the electrical parameters, such as the threshold voltage, compared to other models published elsewhere.

Abstract: In this paper, the threshold voltage and subthreshold slope of strained-Si channel n-MOSFETs are determined, taking into account quantum-mechanical effects, and the effect of bandgap narrowing due to heavy channel doping and the effect of surface roughness at the Si/SiGe heterointerface for ultra thin channels. Quantum-mechanical effects have been incorporated by considering three components, (1) the modified subband energy of 2D inversion layer charges at the silicon dioxide–silicon interface, (2) the increased effective oxide thickness and (3) the altered value of ground state energy due to surface roughness. The analytical results of threshold voltage and threshold voltage difference are presented with reference to unstrained-Si channel for strained-Si MOSFETs by employing poly-Si gate and titanium nitride gate, the work function of which can be varied over a wide range. In addition, we have predicted the dependence of threshold voltage on different values of oxide thickness, channel doping concentration, and on the molar content, x, of Ge in the Si1−xGex virtual substrate. When compared with the theoretical data of Nayfeh et al our analytical results agree more closely with our experimental results and also with measured and simulated data of threshold voltage for a wide range of devices available in the literature. Furthermore, we have calculated the subthreshold slope of strained-Si channel MOSFETs for different amounts of Ge in the SiGe layer.

Abstract: The present study attempts to systematically assess the effect of varying the heat treatment temperature together with the duration of heat treatment on the tribological performance of EN coating and also correlating the same with the microstructural observations. High phosphorous nickel coating is developed in-house over steel substrates. The coatings are subjected to heat treatment at temperatures ranging from 200 to 800 °C for different durations (1–4 h). Suitable microstructural evaluations are carried out to study the morphology, phase structure and composition of the coatings. Hardness and friction-wear tests are carried out in a micro-hardness tester and pin-on-disc tribo-tester respectively. It is observed that heat treatment temperature as well as duration has profound impact on the microstructure of the coating. Iron diffusion and oxide formation is one of the major phenomena occurring at higher heat treatment temperatures. Hardness and wear resistance is found to increase with heat treatment. However, increased temperature (above 600 °C) and duration (4 h) is not found to have much effect on friction and wear behavior of the coating. The oxide layer formed due to high temperature gives rise to a damaged surface with cracks and delamination due to growth stresses. However, the damage is limited to the top surface of the coating which mainly comprises of oxides of nickel and iron. Hardness and wear resistance is not found to be correlated even through the dominant wear mechanism is abrasive in nature.

Abstract: The electrical equivalent circuits of quantum cascade lasers (QCLs) under steady state and under an ac small-signal are developed by employing simplified rate equations for electronic transitions between two levels and the rate equation for photon numbers. Two interactive circuits represent the steady state behaviour and another two coupled circuits model the ac small-signal performance of a QCL. The equivalent circuits are then used for SPICE simulation. The steady state equivalent circuit reproduces the light current curve of QCLs. The ac equivalent circuit yields the intensity modulation response, which matches almost exactly with the curve obtained from reported numerical calculations based on a third-order system model. In addition, the ac model is employed for SPICE simulation to give values of the modulation bandwidth for different values of photon lifetime. The SPICE model gives a slightly different curve for the bandwidth against photon lifetime from the curve plotted using the approximate analytical expression.

Abstract: Electroless nickel coating occurs through an autocatalytic chemical reaction and without the aid of electricity. From tribological perspective, it is recommended due to its high hardness, wear resistance, lubricity and corrosion resistance properties. In this paper electroless Ni-P coatings with high phosphorous weight percentages are developed on mild steel (AISI 1040) substrates. The coatings are subjected to heat treatment at 300°C and 500°C for time durations up to 4 hours. The effect of heat treatment duration on the hardness as well as tribological properties is discussed in detail. Hardness is measured in a micro hardness tester while the tribological tests are carried out on a pin-on-disc tribotester. Wear is reported in the form of wear rates of the sample subjected to the test. As expected, heat treatment of electroless Ni-P coating results in enhancement in its hardness which in turn increases its wear resistance. The present study also finds that duration of heat treatment has quite an effect on the properties of the coating. Increase in heat treatment time in general results in increase in the hardness of the coating. Coefficient of friction is also found to be lesser for the samples heat treated for longer durations (4 hour). However, in case of wear, similar trend is not observed. Instead samples heat treated for 2 to 3 hour display better wear resistance compared to the same heat treated for 4 hour duration. The microstructure of the coating is also carried out to ensure about its proper development. From scanning electron microscopy (SEM), the coating is found to possess the conventional nodular structure while energy dispersive X-ray analysis (EDX) shows that the phosphorous content in the coating to be greater than 9%. This means that the current coating belongs to the high phosphorous category. From X-ray diffraction analysis (XRD), it is found that coating is amorphous in as-deposited condition but transforms into a crystalline structure with heat treatment.

Abstract: A two-dimensional (2D) model for the threshold voltage of the short-channel double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a vertical Gaussian-like doping profile is proposed in this paper. The evanescent mode analysis has been used to solve the 2D Poisson’s equation to obtain the channel potential function of the device. The minimum surface potential has been used to model the threshold voltage of the DG MOSFETs. Threshold voltage variations against channel length for different device parameters have been demonstrated. The validity of the proposed model is shown by comparing the results with the numerical simulation data obtained by using the commercially available ATLAS™, a 2D device simulator from SILVACO.

Abstract: An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Abstract: The paper presents a 2D analytical model for the potential function and threshold voltage of symmetric Double-Gate (DG) MOSFETs with vertical Gaussian doping profile in the channel.

Abstract: This study investigates the effect of incorporating nanoparticles – TiO 2 , Al 2 O 3 , CuO, and multi-walled carbon nanotubes (MWNTs) – within greases Mobilgrease 28 and Uniflor 8623B on their thermal transport and tribological properties. Nanoparticle filler fractions, varying from 0.01 to 0.10 wt%, were homogeneously dispersed within selected greases. Two tribological tests were performed on a four-ball tribotester; ASTM D5183, and the ITeEPib Polish method for testing lubricants under scuffing conditions. Anti-wear properties resulted in up to 20% wear scar diameter (WSD) reduction using a very low filler fraction of 0.01 wt% TiO 2 . For the extreme pressure test, the increase on the load-carrying capacity was found to be ~19% with a filler fraction of 0.05 wt% CuO. A guarded hot-plate method-based apparatus was used in order to characterize thermal conductivity of nanogreases, showing an enhancement of ~28% in thermal conductivity with the addition of 0.10 wt% MWNTs. These results demonstrate the potential of nanoparticle additives for improving thermal properties of greases while decreasing friction and wear of mechanical components.

Abstract: Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.