Photoconductivity in CuInSe2 films

In this paper we propose a general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle. Within this framework we propose algorithms for computing routing solutions using optimal or near optimal number of tracks for several well-known benchmark channels in the two-layer VH. Three-layer HVH, and multi-layer V/sub i/H/sub i/ and V/sub i/H/sub i+1/ routing models. Within the same framework we also design an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models.

A general graph theoretic framework for multi-layer channel routing

Among the emerging technologies Field-Coupled devices like Quantum dot Cellular Automata are one of the most interesting. Of all the practical implementations of this principle NanoMagnet Logic shows many important features, such like a very low power consumption and the feasibility with up-to-date technology. However its working principle, based on the interaction among neighbor cells, is quite different from CMOS circuits. Dedicated design and simulation tools for this technology are necessary to further study this technology, but at the moment there are no such tools available in the scientific scenario.

/pdf/topolinano-nanomagnet-logic-circuits-design-and-simulation-4q5a7bd4ym.pdf

ToPoliNano: NanoMagnet Logic Circuits Design and Simulation

A line capacitance is estimated in consideration of an influence of an adjacent line in rough routing, so that line paths can be determined so as to be free from a timing error. A routing graph is generated from a target integrated circuit, and line paths of cell-to-cell lines are initially determined on the basis of a passage cost set with regard to each of edges of the routing graph. With regard to each edge of the routing graph, the number of cell-to-cell lines passing through the edge is obtained as a line density, and a line capacitance of each line path in view of the influence of an adjacent line is estimated on the basis of the line density. It is verified whether or not there is a timing error with a delay time estimated, and when the integrated circuit does not satisfy a predetermined timing constraint, the line paths are re-determined with the passage cost of each edge allowed to be affected by the line capacitance. Alternatively, allocation to an interconnect layer is changed or a line-to-line distance is increased, so that the integrated circuit can satisfy the timing constraint.

Line path determining method and delay estimating method

Crosstalk minimization is one of the most important high performance aspects in interconnecting VLSI circuits. With advancement of fabrication technology, devices and interconnecting wires are placed in closer proximity and circuits operate at higher frequencies. This results in crosstalk between wire segments. Crosstalk minimization problem for the reserved two-layer Manhattan channel routing is NP-hard, even if the channel instances are free from any vertical constraint (simplest channel instances). In this paper we have developed heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions for simplest as well as general channel instances. In general, the results obtained are highly encouraging.

http://inet.vidyasagar.ac.in:8080/jspui/bitstream/123456789/711/2/JPS10art16.pdf

Algorithms for Reducing Crosstalk in Two-Layer Channel Routing

The channel routing problem in VLSI design is to route a specified interconnection among modules in as small an area as possible. Hashimoto and Stevens (1971) proposed an algorithm for solving the two-layer channel routing problem in the absence of vertical constraints. In this paper, we analyze this algorithm in two different ways. In the first analysis, we show that a graph-theoretic realization, algorithm MCC1, runs in O(m + n + e) time, where m is the size of the channel specification of n nets, and e is the size of the complement of the horizontal constraint graph. In the second analysis, algorithm MCC2, we show that a time complexity of O(m + n log n) can be achieved. Algorithms MCC1 and MCC2 guarantee optimum routing solutions under the multi-layer V/sub i+1/H/sub i/ (i/spl ges/1) routing model, where the horizontal and vertical layers of interconnect alternate. Finally, we consider the problem of minimizing the total net wire length in the V/sub i+1/H/sub i/ (i/spl ges/1) routing model. Given a channel specification and a partition of the set of nets (where the nets within each part of the partition are non-overlapping), we propose an O(m + d/sub max/log d/sub max/) time algorithm for minimizing the total net wire length, subject to the condition that nets from a part of the partition are assigned to the same track. All our solutions use the minimum number of via holes. >

https://ieeexplore.ieee.org/iel2/1063/7689/00320053.pdf

Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic

Minimization of total (vertical) wire length is one of the most important problems in laying out blocks in VLSI physical design. Minimization of wire length not only reduces the cost of physical wiring required, but also reduces the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg, two-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as low total (vertical) wire length as possible. In this paper we develop an efficient heuristic algorithm for appreciably reducing the total wire length in the reserved two-layer no-dogleg Manhattan channel routing model. Experimental results obtained are greatly encouraging.

Achira Pal

Papers

Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic

Algorithms for Reducing Crosstalk in Two-Layer Channel Routing

A graph based algorithm to minimize total wire length in VLSI channel routing

Algorithms for high performance two-layer channel routing