Light emitting diodes reliability review

Market power and strategic interaction in electricity networks

Heat and fluid flow in high-power LED packaging and applications

There is a great interest in wide-bandgap semiconductor devices and most recently in monolithic GaN structures for power electronics applications. In this paper, vertical p-n diodes fabricated on pseudobulk low defect density ( $10^{4}$ – $10^{6}$ cm $^{-2}$ ) GaN substrates are discussed. Homoepitaxial low-pressure metal organic chemical vapor deposition growth of GaN on its native substrate and being able to control and balance the n-type Si doping with background C impurity has allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40 $\mu $ m and net carrier electron concentrations of $4\times 10^{15}$ to $2.5\times 10^{16}$ cm $^{-3}$ . This parameter range is suitable for applications requiring breakdown voltages (BVs) of 600 V–4 kV with a proper edge termination strategy. Measured devices demonstrate near power device figure of merit, that is, differential specific on-resistance ( $R_{{{\textrm {sp}}}}$ ) of 2 m $\Omega $ cm $^{2}$ for a BV of 2.6 kV and 2.95 m $\Omega $ cm $^{2}$ for a 3.7-kV device, respectively. The improvement in the substrate quality over the last few years has resulted in the fabrication of diodes with areas as large as 16 mm $^{2}$ , with BVs exceeding 700 V and pulsed (100 $\mu $ s) currents of 400 A. The structures fabricated are utilized to study in detail the temperature dependency of $I$ – $V$ characteristics, impact ionization and avalanche characteristics, and extract (estimate) modeling parameters such as electron mobility in the GaN $c$ -direction (vertical) and hole minority carrier lifetimes. Some insight into device reliability is also provided.

Vertical Power p-n Diodes Based on Bulk GaN

Light emitting diodes, LEDs, historically have been used for indicators and produced low amounts of heat. The introduction of high brightness LEDs with white light and monochromatic colors have led to a movement towards general illumination. The increased electrical currents used to drive the LEDs have focused more attention on the thermal paths in the developments of LED power packaging. The luminous efficiency of LEDs is soon expected to reach over 80 lumens/W, this is approximately 6 times the efficiency of a conventional incandescent tungsten bulb. Thermal management for the solid-state lighting applications is a key design parameter for both package and system level. Package and system level thermal management is discussed in separate sections. Effect of chip packages on junction to board thermal resistance was compared for both SiC and Sapphire chips. The higher thermal conductivity of the SiC chip provided about 2 times better thermal performance than the latter, while the under-filled Sapphire chip package can only catch the SiC chip performance. Later, system level thermal management was studied based on established numerical models for a conceptual solid-state lighting system. A conceptual LED illumination system was chosen and CFD models were created to determine the availability and limitations of passive air-cooling.

Thermal management of LEDs: Package to system

Thermal effects in packaging high power light emitting diode arrays

A series of harmonic Joule-heating experiments have been employed to determine the thermal conductivities of thin films of pentacene, N,N′-diphenyl−N,N′-di(3-methylphenyl)−(1,1′-biphenyl)-4,4′-diamine, and tris(8-hydroquinolinato)aluminum, three widely used organic semiconductors Room-temperature thermal conductivity values of 051, 024, and 048W∕mK were measured for films of these three compounds, respectively These values are over two orders of magnitude lower than those of inorganic semiconductors While amorphous films were found to display only small thermal conductivity changes over the temperature range of 228–350 K, pentacene exhibited stronger variations that are typical of phonon-phonon scattering observed in polycrystalline semiconductors

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Thermal transport properties of thin films of small molecule organic semiconductors

Raman thermometry is often utilized to measure temperature in gallium nitride (GaN) electronics. However, the accuracy of the technique is subject to errors arising from stresses which develop during device operation as a result of both thermoelastic and inverse piezoelectric effects. To assess the implications of these stresses on Raman thermometry, we investigate the use of the Stokes peak position, linewidth, and Stokes to anti-Stokes intensity ratio to estimate the temperature of GaN devices during operation. Our results indicate that only temperature measurements obtained from the intensity ratio method are independent of these stresses. Measurements using the linewidth, meanwhile, were found to correspond well with those obtained from the intensity ratio through the use of a reference condition which accounted for the stress dependency of this spectral component. These results were then compared to a three dimensional finite element model which yielded a correlation to within 5% between the computat...

Micro-Raman thermometry in the presence of complex stresses in GaN devices

A coupled lattice Boltzmann (LB)–finite-difference (FD) method is used to solve for the heat transport in a two-dimensional domain. The LB method is used to capture relevant phonon physics near a microscopic heat-generation region by solving the Boltzmann transport equation, while a finite-difference model is used to capture the thermal transport at the macroscopic level. The coupling region between the LB and FD domains, which enables multiscale modeling, is discussed. The model is evaluated versus other numerical methods as well as experimental results. In all cases, the multiscale approach yielded results that were accurate to within the experimental uncertainty.

Multiscale Lattice Boltzmann Modeling of Phonon Transport in Crystalline Semiconductor Materials

The capability of gallium nitride (GaN) high power transistors arises, in large part, due to piezoelectric polarizations that induce the formation of a carrier rich two-dimensional electron gas. These polarizations, in turn, are directly related to the strain and hence stress that is present within the transistor. As a consequence, the stress load, as well as its measurement, is extremely important to the optimization of this device class. In response, this study demonstrates a technique to quantify the magnitude of operational thermoelastic stress that evolves in a GaN transistor through simultaneous use of the Raman signal’s Stokes peak position and linewidth. After verifying the technique through comparison with a finite element model, the method is then utilized in the analysis of high electron mobility transistors grown on silicon (Si) and silicon carbide (SiC) substrates. For each series of device, the major stress contributors—thermoelastic, converse piezoelectric, and residual—are acquired and com...

Adam Christensen

Papers

Thermal effects in packaging high power light emitting diode arrays

Thermal transport properties of thin films of small molecule organic semiconductors

Micro-Raman thermometry in the presence of complex stresses in GaN devices

Multiscale Lattice Boltzmann Modeling of Phonon Transport in Crystalline Semiconductor Materials

Assessment of stress contributions in GaN high electron mobility transistors of differing substrates using Raman spectroscopy