Aditi Moudgil

Bio: Aditi Moudgil is an academic researcher from Chitkara University. The author has contributed to research in topics: Low voltage & Application-specific instruction-set processor. The author has an hindex of 3, co-authored 4 publications receiving 24 citations.

Thermal and power aware Internet of Things enable RAM design on FPGA

Abstract: In this work, we are going to use thermal aware approach in random access memory (RAM) design and also testing thermal stability by working on different ambient temperatures 285.15K, 288.15KC, 308.15C, 323.15K, 325.15K and 348.15K. We have observe the compatibility of our device with wireless network by working on different processor frequencies i.e. 1.2 GHz, 1.7 GHz, 2.5 GHz, 3 GHz and 3.6 GHz. There is 67.27% reduction in IOs power, 66.67% reduction in BRAMs power, 18.5% reduction in leakage power, 67.61% reduction in clock power, 100% reduction in logic power, and 65.79% reduction in signal power, and 62.1% reduction in total power, when we scale down operating frequency from 3.6 GHz to 1.2 GHz at 323.15K ambient temperature. In this work, we are using Verilog Hardware Description Language.

GTL based Internet of Things enable processor specific RAM design on 65nm FPGA

Abstract: In this work, we Energy Efficient Internet of Things (IoTs) Enable RAM is presented. In order to make it energy efficient, used Gunning Transceiver Logic (GTL) IO Standard and Gunning Transceiver Logic Plus (GTLP). We used the 4 different members of GTL and GTLP IO standards family and searched the most energy efficient among them. We observed that when we use 3.6 GHz operating frequency, there is 90.2% reduction in I/O power when we used GTL instead of GTLP_DCI. We have inserted a 128-bit IP address in RAM to make internet of things enable RAM. Finally, we operated our IOTs Enable RAM with different operating frequency of I3, I5, I7, Moto-E and Moto-X.

LVCMOS-Based Frequency-Specific Processor Design on 40-nm FPGA

Abstract: This paper shows a power efficient processor design using LVCMOS and HSTL I/O standards. We have compared the performance of our processor through different frequencies. To increase the performance, code of the processor has been remodified by using I/O standards. On remodification of code at different operating frequencies, a significant reduction in logic power, clock power, IO power, signal power and thus total power dissipation is observed. By doing power analysis, the best results are obtained by using LVCMOS12. This paper provides a novel FPGA-based design for power efficient processor.

Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array

Abstract: A real capacitor will have some power dissipation, whereas an ideal capacitor will not dissipate any power. In this paper, we designed a capacitance scaling-based low-power RAM design. Our work aims to analyze how the memory circuit works using capacitance scaling does and varying temperatures. This design is implemented in Verilog. Usually, for the functioning of a device, the junction temperature is below 125 °C. If we scale down frequency from 10 to 4.5 GHz, 2.3 and 1 GHz then there is 42.96, 59.03, and 70.4% reduction, respectively, in total power at 5 pF output load. With the increase in capacitance, there should be the increase in junction temperature. But the novelty of our work is that we can control the effect of capacitance scaling on junction temperature with the help of addition airflow of 500 Linear Feet per Minute (LFM).

A Discussion about Upgrading the Quick Script Platform to Create Natural Language based IoT Systems

Abstract: Objectives: With the advent of AI and IoT, the idea of incorporating smart things/appliances in our day to day life is converting into a reality. The paper discusses the possibilities and potential of designing IoT systems which can be controlled via natural language, with help of Quick Script as a development platform. Methods/Statistical Analysis: Quick Script (or QS) is an open-source, easy to learn tool made by our team of student developers for programming virtual conversational entities. This paper focuses on a discussion about how some improvements can be made in the underlying implementation of QS and the resulting uncomplicated and simple platform which can be used to create natural language based IoT systems. It explores the architecture/design pattern required for creating such systems. Findings: This exploration reveals how the idea of turning a simple NLP tool to handling IoT systems can be implemented, and where all the necessary changes/ additions are to be made. The benefits of this will include sharing the power of controlling and even programming (up to some extent) to the user end. As well as providing a simple intermediary to make communication between man and his machines a little more natural. Application/Improvements: It has always been a fantasy in movies to have appliances and gadgets work according to our speech inputs in real time. We humans have always tried to take complete advantage of technologies for living better and working more productively. The idea behind this paper drives for the same cause. Applications of any natural language based service can be endless–ranging from home to industry. With the speech based interaction, this will even help the physically disabled people.

A Designing of Random Access Memory Using Different IO Standard Technology

Abstract: In this work, we proposed simulation of RAM memory using different IO Standard technologies on 28nm feature size FPGA. LVTTL and Mobile-DDR IO standard is used for designing RAM circuit, power consumption by this Memory has been calculated by applying two different technologies i.e. Mobile-DDR and Low Voltage Transistor- Transistor Logic. Both IO Standards are compared with each other to find out the most power efficient one. We validated our circuit with different IO Standards and on Different frequency range to obtain a most power efficient circuit. In our work, there is 28.05% power reduction when LVTTL is replaced with Mobile-DDR on 1 GHz frequency and 47.93% power reduction at 4GHz operating frequency. To design this energy efficient memory circuit, we are using Verilog as HDL, Xilinx ISE 14.2 simulator with Artix-7 FPGA.