This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs) A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT We present guidelines to optimize the device for high on-to-off current ratio Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs

Effect of Band-to-Band Tunneling on Junctionless Transistors

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logic style is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

/pdf/cmos-logic-design-with-independent-gate-finfets-rdy5ndrp4e.pdf

CMOS logic design with independent-gate FinFETs

An analytical model is proposed to compute the fringe capacitance between two nonoverlapping interconnects in different layers using a conformal mapping technique. With this technique, electric field lines are geometrically approximated to separately model the different capacitive components. These components are finally combined to obtain the equivalent fringe capacitance. Using the aforementioned technique, a model was developed to compute the capacitances of typical interconnect geometries using technology-dependent parameters. The proposed model closely matches with FASTCAP results and significantly reduces the computational complexity and time in calculating the interconnect capacitances

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

The quasi-planar double-gate FinFET has emerged as one of the most likely successors to the classical planar MOSFET for ultimate scalability. Unlike planar devices, its channel width is in the vertical direction; hence it is possible to increase effective channel width (and hence drive current) per unit planar area by increasing fin-height (SOI thickness). This translates directly to improved performance in interconnect-dominated circuits. In this paper we explore the joint V/sub dd/-fin-height-V/sub t/ design space for a 65 nm FinFET SRAM. We report that 69% taller fins can accommodate 18% (140 mV) lower V/sub dd/ as well as 35 % (70 mV) higher V/sub t/ to deliver iso-performance at 87% lower sub-threshold leakage, 50% lower gate leakage, 25% lower dynamic energy, 13% higher static noise margin and 38% higher critical charge for soft-error immunity.

https://www.eecs.wsu.edu/%7Eosman/EE597/FINFET/finfet1.pdf

FinFET SRAM - device and circuit design considerations

https://ir.nctu.edu.tw:443/bitstream/11536/7149/1/000267098700013.pdf

Aditya Bansal

Papers

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

FinFET SRAM - device and circuit design considerations

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability