Adnan Suleiman

Bio: Adnan Suleiman is an academic researcher from University of Texas at San Antonio. The author has contributed to research in topics: Throughput (business) & Discrete cosine transform. The author has an hindex of 2, co-authored 7 publications receiving 43 citations. Previous affiliations of Adnan Suleiman include Cirrus Logic.

A Development and Testing Instrumentation for GPS Software Defined Radio With Fast FPGA Prototyping Support

Abstract: The modernization of global positioning systems (GPS) boosts the development of civil and military applications as accuracy and coverage of receivers continually improve. Recently, software defined radio (SDR) approach for GPS receivers (GPS-SDR) gained attention because of its flexibility for multimode operations in different environments. The SDR receiver developers continually advance algorithmic and/or hardware accelerator solutions. However, they need fast prototyping and testing instrumentation to refine and evaluate high performance multimode receivers. This paper presents a feasibility study of fast prototyping of the GPS receiver accelerators using graphical user interface environments. It also describes a testbed with integrated RF front-ends, GPS simulator, receiver, and assistance support. Particularly, a novel host-target codesign solution is demonstrated using a field programmable gate array (FPGA) peripheral and LabVIEW FPGA tool for a case study of a GPS acquisition module. Distributing tasks between the FPGA target and the personal computer host achieves a high performance solution. The fast prototyped solution is compared with a conventional FPGA and state-of-the-art implementations.

A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

Abstract: The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024-point FFT with 2 processing elements using 45 nm process technology, including area, timing, power and place-and-route results.

Scalable FFT architecture vs. multiple pipeline FFT architectures — Hardware implementation and cost

Abstract: This paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). Hardware comparison to other existing pipeline architecture presented based on implementation of 1024-point FFT with 4 processing elements using 45nm process technology. The proposed architecture is most suitable for handheld and portable multimedia applications

Design method for scalable discrete trigonometric transforms (DTT) with constant geometry

Abstract: In this paper we present a hardware architecture suitable for implementing discrete trigonometric transforms (DTT) including popular fast Discrete Cosine (DCT) and Sine (DST) transforms. The design method is modular and uses predesigned components to construct a transform system. A data shuffle network structure is presented in this work and we will show how it is used in conjunction with a partial column structure to build and compute the transforms. The scalability is based only on the transform size and the number of processing elements (PE). The transform throughput is determined by the number of PE and its associated shuffle network size. In this work we use a scalable DCT-II algorithm with a constant geometry structure to present the design methodology. The design approach can be applied to implement other discrete trigonometric transforms with similar property.

Implementation of scalable interconnect networks for data reordering used in Discrete Trigonometric Transforms (DTT)

Abstract: The number of processing elements (PE) can be reduces significantly using partial column structure to perform Discrete Trigonometric Transform (DTT) computation. Data reordering is required between stages (columns). A scalable interconnect network for both global and local for data reordering is presented in this paper. The network scalability is based on the transform size and the number of processing elements (PE). The structure will reorder data on the fly and eliminate the need of memory. This will help evaluating throughput vs. complexity (cost and area.). Detail analysis of hardware cost will be presented

Towards efficient arithmetic for lattice-based cryptography on reconfigurable hardware

Abstract: In recent years lattice-based cryptography has emerged as quantum secure and theoretically elegant alternative to classical cryptographic schemes (like ECC or RSA). In addition to that, lattices are a versatile tool and play an important role in the development of efficient fully or somewhat homomorphic encryption (SHE/FHE) schemes. In practice, ideal lattices defined in the polynomial ring ℤp[x]/〈xn+1〉 allow the reduction of the generally very large key sizes of lattice constructions. Another advantage of ideal lattices is that polynomial multiplication is a basic operation that has, in theory, only quasi-linear time complexity of ${\mathcal O}(n \log{n})$ in ℤp[x]/〈xn+1〉. However, few is known about the practical performance of the FFT in this specific application domain and whether it is really an alternative. In this work we make a first step towards efficient FFT-based arithmetic for lattice-based cryptography and show that the FFT can be implemented efficiently on reconfigurable hardware. We give instantiations of recently proposed parameter sets for homomorphic and public-key encryption. In a generic setting we are able to multiply polynomials with up to 4096 coefficients and a 17-bit prime in less than 0.5 milliseconds. For a parameter set of a SHE scheme (n=1024,p=1061093377) our implementation performs 9063 polynomial multiplications per second on a mid-range Spartan-6.

Software-Defined Radio GNSS Instrumentation for Spoofing Mitigation: A Review and a Case Study

Abstract: Recently, several global navigation satellite systems (GNSS) emerged following the transformative technology impact of the first GNSS—U.S. global positioning system (GPS). The power level of GNSS signals as measured at earth’s surface is below the noise floor and is consequently vulnerable against interference. Spoofers are smart GNSS-like interferers, which mislead the receivers into generating false position and time information. While many spoofing mitigation techniques exist, spoofers are continually evolving, producing a cycle of new spoofing attacks and counter-measures against them. Thus, upgradability of receivers becomes an important advantage for maintaining their immunity against spoofing. Software-defined radio implementations of a GPS receiver address such flexibility but are challenged by demanding computational requirements of both GNSS signal processing and spoofing mitigation. Therefore, this paper reviews reported SDRs in the context of instrumentation capabilities for both conventional and spoofing mitigation modes. This separation is necessitated by significantly increased computational loads when in spoofing domain. This is demonstrated by a case study budget analysis.

Development of a Real-Time Software-Defined GPS Receiver in a LabVIEW-Based Instrumentation Environment

Abstract: The ubiquitousness of location-based services has proven effective for many applications such as commercial, military, and emergency responders. Software-defined radio (SDR) has emerged as an adequate framework for the development and testing of global navigational satellite systems such as the global position system (GPS). SDR receivers are constantly developing in terms of acceleration factors and accurate algorithms for precise user navigation. However, many SDR options for GPS receivers currently lack real-time operation or could be costly. This paper presents a LabVIEW (LV) and C/C++-based GPS L1 receiver platform with real-time capabilities. The system relies on LV acceleration factors as well as other C/C++ techniques such as dynamic link library integration into LV and parallelizable loop structures, and single instruction, multiple data methods, which leverage host PC multipurpose processors. A hardware testbed is presented for compactness and mobility, as well as software functionality and data flow handling inherent in LV environment. Benchmarks and other real-time results are presented as well as compared with the other state-of-the-art open-source GPS receivers.

A Reconfigurable SDR Transmitter Platform Architecture for Space Modulation MIMO Techniques

Abstract: Space modulation is a group of multiple-input multiple-output (MIMO) techniques that attracted significant research interests lately. However, the aspect of implementation approaches and software defined radio (SDR) has been so far very limited. The aim of this paper is to propose a novel single SDR platform architecture that implements different space modulation techniques using currently available commercial off-the-shelf components. The proposed platform architecture can be dynamically reconfigured to implement different space modulation techniques with marginal to almost no extra hardware overhead. The impact of different hardware components that have to be considered to realize such an implementation is also analyzed and studied.