Ahmad M. Shafiee

Bio: Ahmad M. Shafiee is an academic researcher from Islamic Azad University. The author has contributed to research in topics: Pipeline (computing) & Profiling (information science). The author has an hindex of 2, co-authored 5 publications receiving 17 citations. Previous affiliations of Ahmad M. Shafiee include Islamic Azad University, Isfahan.

An Innovational Intermittent Algorithm in Networks-On-Chip (NOC)

Abstract: Every day human life experiences new equipments more automatic and with more abilities. So the need for faster processors doesn’t seem to finish. Despite new architectures and higher frequencies, a single processor is not adequate for many applications. Parallel processing and networks are previous solutions for this problem. The new solution to put a network of resources on a chip is called NOC (network on a chip). The more usual topology for NOC is mesh topology. There are several routing algorithms suitable for this topology such as XY, fully adaptive, etc. In this paper we have suggested a new algorithm named Intermittent X, Y (IX/Y). We have developed the new algorithm in simulation environment to compare delay and power consumption with elders' algorithms. Keywords—Computer architecture, parallel computing, NOC, routing algorithm.

Application of Improved Artificial Intelligence with Runner-Root Meta-Heuristic Algorithm for Dairy Products Industry: A Case Study

Abstract: As the dairy products have a short consumption period, the accurate prediction of their demand is very important for the dairy industry. Accordingly, this research specifically addresses the predic...

Congestion resistant routing algorithm for a congestion resistant ring road network on chip

Abstract: Ring Road NoC (R2NoC), which was motivated by smooth flow of traffic in interconnected ring roads, is the base for this paper. Router design and routing algorithm for R2NoC is much simpler. In this paper we have developed the R2NOC's algorithm of routing in two ways. One of them is finding the shortest way between source and destination (θ algorithm) and as the second improvement, when we have a congestion or a link is broken, the CR (Congestion Resistant) algorithm will find another way to send the packet and we maintain that this way is shortest safe way and because of that, our algorithm is congestion resistant.

Facing pipeline false dependencies using VRB table

Abstract: The number of physical registers is one of the critical issues of current superscalar out-of-order processors. A system and method for register renaming which allocates physical registers when instructions complete execution is renaming with virtual registers. In this way register pressure is significantly reduced. This method needs two map tables (GMT and PMT) which may be delayed due to the necessity of looking them up. The proposed renaming scheme in this paper provides the advantages of banking the virtual and physical registers and adding two pointers to eliminate the need of any map table as well as free lists for physical and virtual registers.

High-Performance Monitoring Sensors for Home Computer Users Security Profiling

Abstract: Recognising user’s risky behaviours in real-time is an important element of providing appropriate solutions and recommending suitable actions for responding to cybersecurity threats. Employing user modelling and machine learning can make this process automated by requires high-performance intelligent agent to create the user security profile. User profiling is the process of producing a profile of the user from historical information and past details. This research tries to identify the monitoring factors and suggests a novel observation solution to create high-performance sensors to generate the user security profile for a home user concerning the user’s privacy. This observer agent helps to create a decision-making model that influences the user’s decision following real-time threats or risky behaviours.

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

Abstract: Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead.

Asymmetric ring topology for reduced latency in on-chip ring networks

Abstract: An apparatus comprising a chip comprising a plurality of nodes, a first plurality of links connecting the plurality of nodes in a first ring network having a first topology, and a second plurality of links connecting the plurality of nodes in a second ring network having a second topology, wherein the first topology is different than the second topology.