Aida Todri-Sanial

Bio: Aida Todri-Sanial is an academic researcher from University of Montpellier. The author has contributed to research in topics: Carbon nanotube & Neuromorphic engineering. The author has an hindex of 11, co-authored 117 publications receiving 583 citations. Previous affiliations of Aida Todri-Sanial include Centre national de la recherche scientifique & University of California, Santa Barbara.

Energy Autonomous Wearable Sensors for Smart Healthcare: A Review

Abstract: Energy Autonomous Wearable Sensors (EAWS) have attracted a large interest due to their potential to provide reliable measurements and continuous bioelectric signals, which help to reduce health risk factors early on, ongoing assessment for disease prevention, and maintaining optimum, lifelong health quality. This review paper presents recent developments and state-of-the-art research related to three critical elements that enable an EAWS. The first element is wearable sensors, which monitor human body physiological signals and activities. Emphasis is given on explaining different types of transduction mechanisms presented, and emerging materials and fabrication techniques. The second element is the flexible and wearable energy storage device to drive low-power electronics and the software needed for automatic detection of unstable physiological parameters. The third is the flexible and stretchable energy harvesting module to recharge batteries for continuous operation of wearable sensors. We conclude by discussing some of the technical challenges in realizing energy-autonomous wearable sensing technologies and possible solutions for overcoming them.

A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era

Abstract: Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM

Abstract: Spin-transfer torque magnetic random access memory (STT-RAM) is a promising and emerging technology due to its many advantageous features such as scalability, nonvolatility, density, endurance, and fast access speed. However, the operation of STT-RAM is severely affected by environmental factors such as process variations and temperature. As the temperature rockets up in modern computing systems, it is highly desirable to understand thermal impact on STT-RAM operations and reliability. In this paper, a thermal-aware MTJ model, calibrated and validated by experimental measurements, is proposed as the basis for thoroughly thermal aware analysis of a 1T1MTJ STT-RAM cell structure. Using this model, we investigate temperature effect on memory cell access behavior in terms of access latency, energy, and reliability on a 45-nm technology node. Thermal impact on a more advanced 11-nm technology node is also evaluated in the paper. Additionally, we propose a thermal-aware design for STT-RAM sensing circuit using a body-biasing technique, which can enlarge read margin dramatically to enhance read reliability under temperature variations. Moreover, our proposed technique can suppress read disturbance effectively as well. Experimental results show that our proposed sensing circuit can enlarge read margin by 2.47 $\times$ when reading “0” and 3.15 $\times$ when reading “1,” and reduce read disturbance error rate by 55.6% on average.

Addressing the Thermal Issues of STT-MRAM From Compact Modeling to Design Techniques

Abstract: Spin transfer torque magnetic random access memory (STT-MRAM) possesses many desirable properties such as nonvolatility, fast access speed, unlimited endurance, and good compatibility with CMOS fabrication process. ITRS has highlighted the potential of STT-MRAM as one of the candidates for the next-generation universal memory technology. However, both the behaviors of the Magnetic Tunnel Junction (MTJ) and the CMOS access transistor, which are two basic elements of STT-MRAM, are generally temperature dependent, threatening the reliability, and performance of STT-MRAM under thermal fluctuations. To investigate the reliability and performance of STT-MRAM under the temperature variation, we developed a thermal model for the perpendicular magnetic anisotropy MTJ device. With the developed model, thermal behaviors and performance of the hybrid MTJ/CMOS circuits can be characterized and thermal optimization techniques can then be studied. Afterward, a thermal-aware sensing circuit is proposed as a case study to exploit the thermal characteristics for improving STT-MRAM read reliability under the temperature variations. Our simulation results show that the proposed sensing circuit can distinctly reduce the read error rate under thermal fluctuations compared with the state-of-the-art designs.

Editorial in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract: As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Higher-order organization of complex networks

Abstract: Networks are a fundamental tool for understanding and modeling complex systems in physics, biology, neuroscience, engineering, and social science. Many networks are known to exhibit rich, lower-order connectivity patterns that can be captured at the level of individual nodes and edges. However, higher-order organization of complex networks—at the level of small network subgraphs—remains largely unknown. Here, we develop a generalized framework for clustering networks on the basis of higher-order connectivity patterns. This framework provides mathematical guarantees on the optimality of obtained clusters and scales to networks with billions of edges. The framework reveals higher-order organization in a number of networks, including information propagation units in neuronal networks and hub structure in transportation networks. Results show that networks exhibit rich higher-order organizational structures that are exposed by clustering based on higher-order connectivity patterns.

Noisy intermediate-scale quantum algorithms

Abstract: Noisy quantum computers can in principle perform reliable quantum computations, but truly scalable systems require noise levels lower than are presently achieved. Still, moderate-complexity computations can be performed. This review discusses what is possible in this ``noisy intermediate scale'' quantum (NISQ) era. Topic areas include the simulation of many-body physics and chemistry, combinatorial optimization, and machine learning. It is evident that the NISQ era has produced new paradigms for programming that will be built upon as quantum computers are further perfected.