Information Theory and Reliable Communication

We propose a general method for constructing Tanner graphs having a large girth by establishing edges or connections between symbol and check nodes in an edge-by-edge manner, called progressive edge-growth (PEG) algorithm. Lower bounds on the girth of PEG Tanner graphs and on the minimum distance of the resulting low-density parity-check (LDPC) codes are derived in terms of parameters of the graphs. Simple variations of the PEG algorithm can also be applied to generate linear-time encodeable LDPC codes. Regular and irregular LDPC codes using PEG Tanner graphs and allowing symbol nodes to take values over GF(q) (q>2) are investigated. Simulation results show that the PEG algorithm is a powerful algorithm to generate good short-block-length LDPC codes.

Regular and irregular progressive edge-growth tanner graphs

Nanotechnology is the science of understanding matter and the control of matter at dimensions of 100 nm or less. Encompassing nanoscale science, engineering, and technology, nanotechnology involves imaging, measuring, modeling, and manipulation of matter at this level of precision. An important aspect of research in nanotechnology involves precision control and manipulation of devices and materials at a nanoscale, i.e., nanopositioning. Nanopositioners are precision mechatronic systems designed to move objects over a small range with a resolution down to a fraction of an atomic diameter. The desired attributes of a nanopositioner are extremely high resolution, accuracy, stability, and fast response. The key to successful nanopositioning is accurate position sensing and feedback control of the motion. This paper presents an overview of nanopositioning technologies and devices emphasizing the key role of advanced control techniques in improving precision, accuracy, and speed of operation of these systems.

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A Survey of Control Issues in Nanopositioning

Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives.

Reduced-complexity decoding of LDPC codes

The ability to tailor the chemical composition and structure of a surface at the sub-100-nm length scale is important for studying topics ranging from molecular electronics to materials assembly, and for investigating biological recognition at the single biomolecule level. Dip-pen nanolithography (DPN) is a scanning probe microscopy-based nanofabrication technique that uniquely combines direct-write soft-matter compatibility with the high resolution and registry of atomic force microscopy (AFM), which makes it a powerful tool for depositing soft and hard materials, in the form of stable and functional architectures, on a variety of surfaces. The technology is accessible to any researcher who can operate an AFM instrument and is now used by more than 200 laboratories throughout the world. This article introduces DPN and reviews the rapid growth of the field of DPN-enabled research and applications over the past several years.

Applications of dip-pen nanolithography.

Efficient implementations of the sum-product algorithm (SPA) are presented for decoding low-density parity-check (LDPC) codes using log-likelihood ratios (LLR) as messages between symbol and parity-check nodes. Various reduced-complexity derivatives of the LLR-SPA are proposed. Both serial and parallel implementations are investigated, leading to trellis and tree topologies, respectively. Furthermore, by exploiting the inherent robustness of LLRs, it is shown, via simulations, that coarse quantization tables are sufficient to implement complex core operations with negligible or no loss in performance. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate design point in high-speed applications from a performance, latency and computational complexity perspective.

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Efficient implementations of the sum-product algorithm for decoding LDPC codes

Ultrahigh storage densities of up to 1 Tb/in./sup 2/ or more can be achieved by using local-probe techniques to write, read back, and erase data in very thin polymer films. The thermomechanical scanning-probe-based data-storage concept called Millipede combines ultrahigh density, small form factor, and high data rate. After illustrating the principles of operation of the Millipede, a channel model for the analysis of the readback process is introduced, and analytical results are compared with experimental data. Furthermore, the arrangement of data-storage fields as well as dedicated fields for servo and timing control is discussed, and system aspects related to the readback process, multiplexing, synchronization, and position-error-signal generation for tracking are introduced. Finally, the application of (d,k) modulation coding as a means to further increase areal density is presented, and the effect on the user data rates discussed.

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"Millipede": a MEMS-based scanning-probe data-storage system

Today's data storage systems are increasingly adopting low-cost disk drives that have higher capacity but lower reliability, leading to more frequent rebuilds and to a higher risk of unrecoverable media errors. We propose an efficient intradisk redundancy scheme to enhance the reliability of RAID systems. This scheme introduces an additional level of redundancy inside each disk, on top of the RAID redundancy across multiple disks. The RAID parity provides protection against disk failures, whereas the proposed scheme aims to protect against media-related unrecoverable errors. In particular, we consider an intradisk redundancy architecture that is based on an interleaved parity-check coding scheme, which incurs only negligible I/O performance degradation. A comparison between this coding scheme and schemes based on traditional Reed--Solomon codes and single-parity-check codes is conducted by analytical means. A new model is developed to capture the effect of correlated unrecoverable sector errors. The probability of an unrecoverable failure associated with these schemes is derived for the new correlated model, as well as for the simpler independent error model. We also derive closed-form expressions for the mean time to data loss of RAID-5 and RAID-6 systems in the presence of unrecoverable errors and disk failures. We then combine these results to characterize the reliability of RAID systems that incorporate the intradisk redundancy scheme. Our results show that in the practical case of correlated errors, the interleaved parity-check scheme provides the same reliability as the optimum, albeit more complex, Reed--Solomon coding scheme. Finally, the I/O and throughput performances are evaluated by means of analysis and event-driven simulation.

A new intra-disk redundancy scheme for high-reliability RAID storage systems in the presence of unrecoverable errors

A new reduced-complexity decoding algorithm for low-density parity-check codes that operates entirely in the log-likelihood domain is presented. The computationally expensive check-node updates of the sum-product algorithm are simplified by using a difference-metric approach on a two-state trellis and by employing the dual-max approximation. The dual-max approximation is further improved by using a correction factor that allows the performance to approach that of full sum-product decoding.

Ajay Dholakia

Papers

Reduced-complexity decoding of LDPC codes

Efficient implementations of the sum-product algorithm for decoding LDPC codes

"Millipede": a MEMS-based scanning-probe data-storage system

A new intra-disk redundancy scheme for high-reliability RAID storage systems in the presence of unrecoverable errors

Reduced-complexity decoding algorithm for low-density parity-check codes