Akram Ben Ahmed

Bio: Akram Ben Ahmed is an academic researcher from Keio University. The author has contributed to research in topics: Fault tolerance & Network on a chip. The author has an hindex of 12, co-authored 38 publications receiving 438 citations. Previous affiliations of Akram Ben Ahmed include University of Aizu & National Institute of Advanced Industrial Science and Technology.

LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture

Abstract: Despite the higher scalability and parallelism integration offered by 2D-Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs). Recently, merging NoC to the third dimension (3D-NoC) has been proposed as a promising solution offering lower power consumption and higher speed. One of the most important design choices for 3D-NoC implementation is the routing algorithm, as it controls the path decision that a flit has tofollow while traveling along the network. This has a direct impact on the overall system performance. In this paper, we present an efficient routing algorithm for 3D-NoC named Look-Ahead-XYZ (LA-XYZ). This algorithm aims to minimize the communication latency and power consumption while enhancing the system throughput. Comparison results with systems adopting two dimensional routing showed that, using JPEG encoder and Matrix applications, LA-XYZ reduces the communication latency with up to 44.9% and enhances the throughput that can reach the 45.3% while observing an average 15.9% reduction in terms of dynamic power.

Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

Abstract: Despite the higher scalability and parallelism integration offered by Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large-scale Systems-on-Chip (SoCs), due to limitations such as high power consumption, high-cost communication, and low throughput. Recently, extending 2D-NoC to the third dimension (3D-NoC) has been proposed to deal with these problems; however, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault tolerant to transient malfunctions or permanent physical damages. In this paper, we propose a low-latency, high-throughput, and fault-tolerant routing algorithm named Look-Ahead-Fault-Tolerant (LAFT). LAFT reduces the communication latency and enhances the system performance while maintaining a reasonable hardware complexity and ensuring fault tolerance. We implemented the proposed algorithm on a real 3D-NoC architecture (3D-OASIS-NoC) and prototyped it on FPGA, then we evaluated its performance over various applications. Evaluation results show that the proposed algorithm efficiently reduces the communication latency that can reach an average of 38 % and 16 %, when compared to conventional XYZ and our early designed Look-Ahead-XYZ routing algorithms, respectively, and enhances the throughput with up to 46 % and 29 %.

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

Abstract: During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the shared-bus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4x4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput. To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.

A Survey on Industrial Information Integration 2016–2019

Abstract: Industrial information integration engineering (IIIE) is a set of foundational concepts and techniques that facilitate the industrial information integration process. In recent years, many applicat...

LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture

Abstract: Despite the higher scalability and parallelism integration offered by 2D-Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs). Recently, merging NoC to the third dimension (3D-NoC) has been proposed as a promising solution offering lower power consumption and higher speed. One of the most important design choices for 3D-NoC implementation is the routing algorithm, as it controls the path decision that a flit has tofollow while traveling along the network. This has a direct impact on the overall system performance. In this paper, we present an efficient routing algorithm for 3D-NoC named Look-Ahead-XYZ (LA-XYZ). This algorithm aims to minimize the communication latency and power consumption while enhancing the system throughput. Comparison results with systems adopting two dimensional routing showed that, using JPEG encoder and Matrix applications, LA-XYZ reduces the communication latency with up to 44.9% and enhances the throughput that can reach the 45.3% while observing an average 15.9% reduction in terms of dynamic power.