A
Al Davis
Researcher at University of Utah
Publications - 65
Citations - 3908
Al Davis is an academic researcher from University of Utah. The author has contributed to research in topics: Memory controller & Interleaved memory. The author has an hindex of 29, co-authored 64 publications receiving 3714 citations. Previous affiliations of Al Davis include Hewlett-Packard.
Papers
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Journal ArticleDOI
Corona: System Implications of Emerging Nanophotonic Technology
Dana M. Vantrease,Robert Schreiber,Matteo Monchiero,Moray McLaren,Norman P. Jouppi,Marco Fiorentino,Al Davis,Nathan Binkert,Raymond G. Beausoleil,Jung Ho Ahn +9 more
TL;DR: This work believes that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously reducing power.
Proceedings ArticleDOI
HyperX: topology, routing, and packaging of efficient large-scale networks
TL;DR: This work considers an extension of the hypercube and flattened butterfly topologies, the HyperX, and gives an adaptive routing algorithm, DAL, to take advantage of high-radix switch components that integrated photonics will make available.
Proceedings ArticleDOI
Rethinking DRAM design and organization for energy-constrained multi-cores
Aniruddha N. Udipi,Naveen Muralimanohar,Niladrish Chatterjee,Rajeev Balasubramonian,Al Davis,Norman P. Jouppi +5 more
TL;DR: This paper examines three primary innovations in DRAM chip microarchitecture that lead to a dramatic reduction in the energy and storage overheads for reliability, and further penalizes the cost-per-bit metric by adding a checksum feature to each cache line.
Proceedings ArticleDOI
Impulse: building a smarter memory controller
John B. Carter,Wilson C. Hsieh,Leigh Stoller,M. Swanson,Lixin Zhang,Erik Brunvand,Al Davis,Chen-Chi Kuo,R. Kuramkote,Michael Parker,Lambert Schaelicke,Terry Tateyama +11 more
TL;DR: The design of the Impulse architecture is described, and how an Impulse memory system can be used to improve the performance of memory-bound programs is shown, which improves performance for the NAS conjugate gradient benchmark by 67%.
Proceedings ArticleDOI
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
Seth H. Pugsley,Jeffrey Jestes,Huihui Zhang,Rajeev Balasubramonian,Vijayalakshmi Srinivasan,Alper Buyuktosunoglu,Al Davis,Feifei Li +7 more
TL;DR: A number of key elements necessary in realizing efficient NDC operation are described and evaluated, including low-EPI cores, long daisy chains of memory devices, and the dynamic activation of cores and SerDes links.