Alain Claverie

Bio: Alain Claverie is an academic researcher from Centre national de la recherche scientifique. The author has contributed to research in topics: Ion implantation & Silicon. The author has an hindex of 37, co-authored 247 publications receiving 5126 citations.

Energetics of self-interstitial clusters in si

Abstract: The transient supersaturation in a system undergoing Ostwald ripening is related to the cluster formation energy ${E}_{\mathrm{fc}}$ as a function of cluster size $n$. We use this relation to study the energetics of self-interstitial clusters in Si. Measurements of transient enhanced diffusion of B in Si-implanted Si are used to determine $S(t)$, and inverse modeling is used to derive ${E}_{\mathrm{fc}}(n)$. For clusters with $ng15$, ${E}_{\mathrm{fc}}\ensuremath{\approx}0.8\mathrm{eV}$, close to the fault energy of ${113}$ defects. For clusters with $nl10$, ${E}_{\mathrm{fc}}$ is typically 0.5 eV higher, but stabler clusters exist at $n\ensuremath{\approx}4$ ( ${E}_{\mathrm{fc}}\ensuremath{\approx}1.0\mathrm{eV}$) and $n\ensuremath{\approx}8$ ( ${E}_{\mathrm{fc}}\ensuremath{\approx}0.6\mathrm{eV}$).

Ostwald ripening of end-of-range defects in silicon

Abstract: End-of-range (EOR) defects are interstitial type dislocation loops which nucleate just beneath the crystalline/amorphous (c/a) interface formed by ion implantation in Si, after the preamorphization of the substrate, and during the ramping-up of the anneal. They originate from the presence of a high supersaturation of “excess” Si self-interstitial atoms located just beneath the c/a interface. Upon annealing, the mean radius of the defects increases while their density decreases through the exchange of Si self-interstitial atoms between the loops. The number of interstitials stored in the loops stays constant. For sufficiently high thermal budgets, when the nucleation is finished, and when the local equilibrium between extended and point defects is established, the coarsening of the EOR defects can be modeled through the Ostwald ripening theory applied to the dislocation loops geometry. Indeed, and as expected from the theory, the square of the mean radius of the loop population increases with time while the loop density decreases proportional to 1/t. Furthermore, the theoretical function describing the size distributions perfectly matches the time evolution of the experimental stack histograms, for different annealing temperatures. During the asymptotic steady-state coarsening regime, the activation energy for the loop coarsening is 4.4 eV, which is in the range of values given in the literature for self-diffusion in Si. Nevertheless, an activation energy of about 1–2 eV is found during the transient period preceding the local equilibrium, i.e., in the range of the migration energy of self-interstitials. The limiting phenomenon for the loop growth appears to be diffusion, since it is the hypothesis that leads to the best fit between theory and experiment. An estimate of DiCi* has been derived from the growth laws of the EOR defects. A value of about 1.8×107 cm−1 s−1 at 1000 °C is obtained and compares well with the values given in the literature.

Direct mapping of strain in a strained silicon transistor by high-resolution electron microscopy.

Abstract: Aberration-corrected high-resolution transmission electron microscopy (HRTEM) is used to measure strain in a strained-silicon metal-oxide-semiconductor field-effect transistor. Strain components parallel and perpendicular to the gate are determined directly from the HRTEM image by geometric phase analysis. ${\mathrm{Si}}_{80}{\mathrm{Ge}}_{20}$ source and drain stressors lead to uniaxial compressive strain in the Si channel, reaching a maximum value of $\ensuremath{-}1.3%$ just below the gate oxide, equivalent to 2.2 GPa. Strain maps obtained by linear elasticity theory, modeled with the finite-element method, agree with the experimental results to within 0.1%.

Optical visualization and electrical characterization of fast-rising pulsed dielectric barrier discharge for airflow control applications

Abstract: Flow control consists of manipulating flows in an effective and robust manner to improve the global performances of transport systems or industrial processes. Plasma technologies, and particularly surface dielectric barrier discharge (DBD), can be a good candidate for such purpose. The present experimental study focuses on optical and electrical characterization of plasma sheet formed by applying a pulse of voltage with rising and falling periods of 50 ns for a typical surface DBD geometry. Positive and negative polarities are compared in terms of current behavior, deposited energy, fast-imaging of the plasma propagation, and resulting modifications of the surrounding medium by using shadowgraphy acquisitions. Positive and negative pulses of voltage produce streamers and corona type plasma, respectively. Both of them result in the production of a localized pressure wave propagating in the air with a speed maintained at 343 m/s (measurements at room temperature of 20 °C). This suggests that the produced pressure wave can be considered as a propagating sound wave. The intensity of the pressure wave is directly connected to the dissipated energy at the dielectric wall with a linear increase with the applied voltage amplitude and a strong dependence toward the rising time. At constant voltage amplitude, the pressure wave is reinforced by using a positive pulse. The present investigation also reveals that rising and decaying periods of a single pulse of voltage result in two distinct pressure waves. As a result, superposition or successive pressure wave can be produced by adjusting the width of the pulse.

Frontiers of silicon-on-insulator

Abstract: Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Memory effects in complex materials and nanoscale systems

Abstract: Memory effects are ubiquitous in nature and are particularly relevant at the nanoscale where the dynamical properties of electrons and ions strongly depend on the history of the system, at least within certain time scales. We review here the memory properties of various materials and systems which appear most strikingly in their non-trivial, time-dependent resistive, capacitative and inductive characteristics. We describe these characteristics within the framework of memristors, memcapacitors and meminductors, namely memory-circuit elements with properties that depend on the history and state of the system. We examine basic issues related to such systems and critically report on both theoretical and experimental progress in understanding their functionalities. We also discuss possible applications of memory effects in various areas of science and technology ranging from digital to analog electronics, biologically inspired circuits and learning. We finally discuss future research opportunities in the field.

Defect identification in semiconductors with positron annihilation: Experiment and theory

Abstract: Positron annihilation spectroscopy is particularly suitable for studying vacancy-type defects in semiconductors. Combining state-of-the-art experimental and theoretical methods allows for detailed identification of the defects and their chemical surroundings. Also charge states and defect levels in the band gap are accessible. In this review the main experimental and theoretical analysis techniques are described. The usage of these methods is illustrated through examples in technologically important elemental and compound semiconductors. Future challenges include the analysis of noncrystalline materials and of transient defect-related phenomena.

Nanoscale holographic interferometry for strain measurements in electronic devices

Abstract: Strained silicon is now an integral feature of the latest generation of transistors and electronic devices because of the associated enhancement in carrier mobility. Strain is also expected to have an important role in future devices based on nanowires and in optoelectronic components. Different strategies have been used to engineer strain in devices, leading to complex strain distributions in two and three dimensions. Developing methods of strain measurement at the nanoscale has therefore been an important objective in recent years but has proved elusive in practice: none of the existing techniques combines the necessary spatial resolution, precision and field of view. For example, Raman spectroscopy or X-ray diffraction techniques can map strain at the micrometre scale, whereas transmission electron microscopy allows strain measurement at the nanometre scale but only over small sample areas. Here we present a technique capable of bridging this gap and measuring strain to high precision, with nanometre spatial resolution and for micrometre fields of view. Our method combines the advantages of moire techniques with the flexibility of off-axis electron holography and is also applicable to relatively thick samples, thus reducing the influence of thin-film relaxation effects.