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Alberto Cestero
Researcher at GlobalFoundries
Publications - 6
Citations - 65
Alberto Cestero is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Logic gate & Logic family. The author has an hindex of 4, co-authored 6 publications receiving 46 citations.
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Journal ArticleDOI
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Janakiraman Viraraghavan,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,Steven Burns,Rajesh R. Tummuru,Herbert L. Ho,Alberto Cestero,Norbert Arnold,Babar A. Khan,Toshiaki Kirihata,Subramanian S. Iyer +21 more
TL;DR: A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell that enables a high voltage gain of a power-gated inverter at mid-level input voltage.
Journal ArticleDOI
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
Balaji Jayaraman,Derek H. Leu,Janakiraman Viraraghavan,Alberto Cestero,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer +12 more
TL;DR: The design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity is described and high-temperature stress results show a projected data retention of 10 years at 125 °C.
Proceedings ArticleDOI
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
Janakiraman Viraraghavan,Derek H. Leu,Balaji Jayaraman,Alberto Cestero,Robert E. Kilker,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer +13 more
TL;DR: An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity.
Proceedings ArticleDOI
A high-density logic-on-logic 3DIC design using face-to-face hybrid wafer-bonding on 12nm FinFET process
Saurabh Sinha,S. Hung,Daniel Fisher,Xiaoqing Xu,C. Chao,Pranavi Chandupatla,F. Frederick,H. Perry,Daniel Smith,Alberto Cestero,John M. Safran,V. Ayyavu,Mudit Bhargava,Rahul Mathur,D. Prasad,Robert Katz,A. Kinsbruner,John J. Garant,Jorge Lubguban,Sarah H. Knickerbocker,V. Soler,Brian Cline,R. Christy,T. McLaurin,Norman Robson,Daniel Berger +25 more
TL;DR: In this article, a high-density 3D test-vehicle with synchronous cache coherent mesh interconnect design (Arm Neoverse® CMN-600) operational at frequencies up to 2.4 GHz and partitioned in 3D using 5.76µm pitch face-to-face wafer-bond 3D connections is presented.
Journal ArticleDOI
14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing
Eric D. Hunt-Schroeder,Darren L. Anand,John A. Fifield,Michael Roberge,Dale Pontius,Mark Jacunski,Kevin Batson,Matthew Deming,Faraz Khan,Dan Moy,Alberto Cestero,Robert Katz,Z. Chbili,Edmund Banghart,L. Jiang,Balaji Jayaraman,Rajesh R. Tummuru,Ramesh Raghavan,Amit Mishra,Norman Robson,Toshiaki Kirihata +20 more
TL;DR: Hardware qualification certifies the OTPM to a 10-year 105 °C data retention specification and <3 PPM end of life bit error rate pre-ECC.