Showing papers by "Alberto Sangiovanni-Vincentelli published in 1983"

Relaxation-based electrical simulation

Abstract: Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective analysis of circuits containing a few hundred transistors or less. Because of the need to verify the performance of larger circuits, many users have successfully simulated circuits containing thousands of transistors despite the cost. Recently, a new class of algorithms has been applied to the electrical IC simulation problem. New simulators using these methods provide accurate waveform information with up to two orders of magnitude speed improvement for large circuits. These programs use relaxation methods for the solution of the set of ordinary differential equations, which describe the circuit under analysis, rather than the direct sparse-matrix methods on which standard circuit simulators are based. In this paper, the techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored. Both the advantages and the limitations of these techniques for the analysis of large IC's are described.

Relaxation-Based Electrical Simulation

Abstract: Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective analysis of circuits containing a few hundred transistors or less. Because of the need to verify the performance of larger circuits, many users have successfully simulated circuits containing thousands of transistors despite the cost.Recently, a new class of algorithms has been applied to the electrical IC simulation problem. New simulators using these methods provide accurate waveform information with up to two orders of magnitude speed improvement for large circuits. These programs use relaxation methods for the solution of the set of ordinary differential equations, which describe the circuit under analysis, rather than the direct sparse-matrix methods on which standard circuit simulators are based.In this paper, the techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored. Both the advantages and the limitations of these techniques for the analysis of large IC's are described.

Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications

Abstract: Programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular, we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.

Pleasure: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays

Abstract: Programmable Logic Arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.

Solution of piecewise- linear ordinary differential equations using waveform relaxation and Laplace transforms

Abstract: Piecewise-linear (PWL) functions are frequently used to describe the nonlinear branch equations of nonlinear devices in LSI circuits. New techniques for the solution of the differential equations describing the behavior of piecewise-linear circuits will be presented. These techniques are based on the waveform relaxation method to decouple the system equations and Laplace transform techniques to solve the decoupled equations. Several desirable features of the resulting algorithm are discussed.

Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits

Abstract: Symmetric displacement techniques for the timing analysis of VLSI circuits are introduced. Their numerical properties such as stability and accuracy are investigated on different classes of circuits.

Solution of piecewise-linear ordinary differential equations using waveform relaxation and laplace transforms

Abstract: Piecewise-linear (PWL) functions are frequently used to describe the nonlinear branch equations of nonlinear devices in LSI circuits. New techniques for the solution of the differential equations describing the behavior of piecewise-linear circuits will be presented. These techniques are based on the waveform relaxation method to decouple the system equations and Laplace transform techniques to solve the decoupled equations. Several desirable features of the resulting algorithm are discussed.

Solution of piecewise-linear ordinary differential equations using waveform relaxation and Laplace transforms

Abstract: Piecewise-linear (PWL) functions are frequently used to describe the nonlinear branch equations of nonlinear devices in LSI circuits. New techniques for the solution of the differential equations describing the behavior of piecewise-linear circuits will be presented. These techniques are based on the waveform relaxation method to decouple the system equations and Laplace transform techniques to solve the decoupled equations. Several desirable features of the resulting algorithm are discussed.

RELAX: a new circuit simulator for large scale MOS integrated circuits

Abstract: Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method 1 which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.