Showing papers by "Alberto Sangiovanni-Vincentelli published in 1985"

The TimberWolf placement and routing package

Abstract: TimberWolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing, have been developed. Experimental results on industrial circuits show that area savings over existing layout programs ranging from 15 to 62% are possible.

Optimal State Assignment for Finite State Machines

Abstract: Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as deterministic synchronous Finite State Machines (FSM's), and we consider a regular and structured implementation by means of Programmable Logic Arrays (PLA's) and feedback registers. State assignment, i.e., binary encoding of the internal states of the finite state machine, affects substantially the silicon area taken by such an implementation. Several state assignment techniques have been proposed in the past. However, to the best of our knowledge, no Computer-Aided Design tool is in use today for an efficient encoding of control logic. We propose an algorithm for optimal state assignment. Optimal state assignment is based on an innovative strategy: logic minimization of the combinational component of the finite state machine is applied before state encoding. Logic minimization is performed on a symbolic (code independent) description of the finite state machine. The minimal symbolic representation defines the constraints of a new encoding problem, whose solutions are the state assignments that allow the implementation of the PLA with at most as many product-terms as the cardinality of the minimal symbolic representation. In this class, an optimal encoding is one of minimal length satisfying these constraints. A heuristic algorithm constructs a solution to the constrained encoding problem. The algorithm has been coded in a computer program, KISS, and tested on several examples of finite state machines. Experimental results have shown that the method is an effective tool for designing finite state machines.

Convergence and finite-time behavior of simulated annealing

Abstract: Simulated Annealing is a randomized algorithm which has been proposed for finding globally optimum least-cost configurations in large NP-complete problems with cost functions which may have many local minima. A theoretical analysis of Simulated Annealing based on its precise model, a time-inhomogeneous Markov chain, is presented. An annealing schedule is given for which the Markov chain is strongly ergodic and the algorithm converges to a global optimum. The finite-time behavior of Simulated Annealing is also analyzed and a bound obtained on the departure of the probability distribution of the state at finite time from the optimum. This bound gives an estimate of the rate of convergence and insights into the conditions on the annealing schedule which gives optimum performance.

A New Symbolic Channel Router: YACR2

Abstract: YACR2 is a channel router that minimizes the number of through vias in addition to the area used to complete the routing in a two-layer channel. It can route channels with cyclic constraints and uses a virtual grid. YACR2 uses preferably one layer for the horizontal segments of the nets and the other for the vertical ones but it may require the routing of a few horizontal segments in the second layer. Experimentally YACR2 performs better than any of the channel routers proposed thus far both in terms of area used and through vias. It routed the Deutsch Difficult Example in density with substantially less vias than Burstein's hierarchical router and with the default parameter values in less than 3 s of CPU time on a VAX 11/780.

PLATYPUS: A PLA Test Pattern Generation Tool

Abstract: PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLAs which is interfaced with other existing PLA tools such as the constrained/unconstrained, simple/multiple folding program PLEASURE and the logic minimizer ESPRESSO II-C developed at the University of California at Berkeley. PLATYPUS uses biased random test generation as a quick preprocess followed by a deterministic test generation process to achieve the best balance between efficient run time and test set minimality. The algorithm adopted in the deterministic phase is exact, i.e., it achieves the highest possible test coverage by generating a test for every testable fault. Powerful heuristics are introduced in the area of fault processing order, backend fault simulation, “don't-care” bit fixing, and on-the-fly test compaction to achieve the best performance of PLATYPUS. The deterministic test generation algorithm is based on both complementation and tautology check of a logic cover. Both complementation and tautology check are performed by an advanced method used in the logic minimizer ESPRESSO-II. PLATYPUS supports both folded and unfolded PLAs, and both crosspoint and stuck-at fault models. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLAs.

Waveform relaxation techniques and their parallel implementation

Abstract: Because of the high cost of fabricating an Integrated Circuit(IC), it is important to verify the design using simulation. There are a wide variety of techniques for simulating integrated circuit designs, but the most accurate is to construct the system of nonlinear ordinary differential equations that describe a given circuit, and solve the system with a numerical integration method. This approach, referred to as circuit simulation, is computationally expensive, particularly when applied to large circuits. To reduce the computation time required to simulate large MOS circuits, new numerical integration algorithms based on relaxation techniques have been developed. These techniques can reduce the simulation time as much as an order of magnitudes over standard circuit simulation programs. In addilion, they are particularly suited for parallel implementation. In this paper we will focus on the Waveform Relaxation (WR) family of algorithms. Algorithms in this family will be reviewed, convergence theorems will be offered, and their implementation on a parallel processor presented.