Showing papers by "Alberto Sangiovanni-Vincentelli published in 1988"

Logic verification using binary decision diagrams in a logic synthesis environment

Abstract: The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed. Combinational logic verification involves checking two networks for functional equivalence. Techniques that flatten networks or use cube enumeration and simulation cannot be used with functions that have very large cube covers. Binary decision diagrams (BDDs) are canonical representations for Boolean functions and offer a technique for formal logic verification. However, the size of BDDs is sensitive to the variable ordering. Ordering strategies based on the network topology are considered. Using these strategies with BDDs, it has been possible to carry out formal verification for a larger set of networks than with existing verification systems. The present method proved significantly faster on the benchmark set of examples tested. >

DELIGHT.SPICE: an optimization-based system for the design of integrated circuits

Abstract: DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of electronic circuits automatically to improve their performance criteria and to study complex tradeoffs between multiple competing objectives, while simultaneously satisfying multiple-constraint specifications. The optimization runs much more efficiently than previously because the SPICE program used has been enhanced to perform DC, AC, and transient sensitivity computation. Industrial analog and digital circuits have been redesigned using this tool, yielding substantial improvement in circuit performance. >

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations

Abstract: The problem of state assignment for synchronous finite-state machines (FSM), targeted towards multilevel combinational logic and feedback register implementations, are addressed. The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize the number of literals in the resulting combinational logic network after multilevel logic optimization. Results over a wide range of benchmarks which prove the efficacy of the proposed techniques are presented. Literal counts averaging 20%-40% less than other state-assignment programs have been obtained. >

Multi-level logic minimization using implicit don't cares

Abstract: An approach is described for the minimization of multilevel logic circuits. A multilevel representation of a block of combinational logic is defined, called a Boolean network. A procedure is then proposed, called ESPRESSOMLD, to transform a given Boolean network into a prime, irredundant, and R-minimal form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Theorems are given that prove the correctness of the proposed procedure. Finally, it is shown that prime and irredundant multilevel logic circuits are 100% testable for input and output single-stuck faults, and that these tests are provided as a byproduct of the minimization. >

Test generation for sequential circuits

Abstract: An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state machines with a large number of states have been successfully generated using reasonable amounts of CPU time and close-to-maximum possible fault coverages have been obtained. For very large sequential circuits, an incomplete scan-design approach to test generation has been developed. The deterministic test generation algorithm is again used to generate test for faults in the modified circuit. All irredundant faults can be detected as in the complete scan design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value-in general, a tradeoff exists between the number of memory elements required to be made scannable and the maximum allowed length of the test sequence. >

Optimization-based transistor sizing

Abstract: A combined heuristic and mathematical programming approach to transistor sizing is presented. A fast heuristic algorithm is used to obtain an initial sizing of the circuit and convert the transistor sizing problem into a nonlinear optimization problem. The problem is then solved, in spaces of reduced dimensionality, by mathematical programming techniques. To cope with the nondifferentiability of the circuit delays, the concept of generalized gradients is proposed to compute the delay sensitivities. Experiments justify the use of this sensitivity computation technique and show that the approach is a good compromise between the speed of the heuristic algorithm and the power of mathematical programming. >

Timing optimization of combinational logic

Abstract: An algorithm for speeding up combinational logic with minimal area increase is presented. A static timing analyzer is used to identify the critical paths. Then a weighted min-cut algorithm is used to determine the subset of nodes to be resynthesized. This subset is selected so that the speedup is achieved with minimal area increase. Resynthesis is done by selectively collapsing the logic along the critical paths and then decomposing the collapsed nodes to minimize the critical delay. This process is iterated until either the timing requirements are satisfied or no further improvement can be made. The algorithm has been implemented and tested on many design examples with promising results. >

Efficient Parallel Learning Algorithms for Neural Networks

Abstract: Parallelizable optimization techniques are applied to the problem of learning in feedforward neural networks. In addition to having superior convergence properties, optimization techniques such as the Polak-Ribiere method are also significantly more efficient than the Backpropagation algorithm. These results are based on experiments performed on small boolean learning problems and the noisy real-valued learning problem of hand-written character recognition.

Applying harmonic balance to almost-periodic circuits

Abstract: A new Fourier transform algorithm for almost-periodic functions (the APFT) is developed. It is both efficient and accurate. Unlike previous attempts to solve this problem, the new algorithm does not constrain the input frequencies and uses the theoretical minimum number of time points. Also presented is a particularly simple derivation of harmonic Newton (the algorithm that results when Newton's method is applied to solve the harmonic balance equations) using the APFT; this derivation uses the same matrix representation used in the derivation of the APFT. Since the APFT includes the DFT (discrete Fourier transform) as a special case, all results are applicable to both the periodic and almost-periodic forms of harmonic Newton. >

An incomplete scan design approach to test generation for sequential machines

Abstract: An incomplete scan design approach to sequential test generation is presented. This approach represents a significant departure from previous methods. First, using an efficient sequential testing algorithm, test sequences are generated for a large number of possible faults in the given sequential circuit. A minimal subset of memory elements is then found, which if made observable and controllable will result in easy detection of the sequentially redundant and irredundant but difficult-to-defect faults. The deterministic test generation algorithm is again used to generate tests for these faults in the modified circuit (the circuit with the identified memory elements made scannable). Detection of all irredundant faults can be guaranteed as in the complete scan design case, but at significantly less area and performance cost. >

An envelope-following method for the efficient transient simulation of switching power and filter circuits

Abstract: The transient behavior of circuits like switching power converters and switched capacitor filters are expensive to simulate because they are clocked at a frequency whose period is orders of magnitude smaller than the time interval of interest to the designer. It is possible to reduce the simulation time without compromising accuracy by exploiting the fact that the behavior of such a circuit in a given high-frequency clock cycle is similar, but not identical, to its behavior in the preceding and following cycles. In particular, the envelope of the high-frequency clock can be followed by accurately computing the circuit behavior over occasional cycles. The authors describe the implementation of an envelope-following method that is particularly efficient for switching power and filter circuits, and they present results demonstrating the method's effectiveness. >

ECSTASY: a new environment for IC design optimization

Abstract: Interfacing to SPICE3 with sensitivity computation capability, ECSTASY features a forms-based, menu-driven user interface for problem formulation and user interaction, superlinearly convergent gradient-based algorithms, and a robust controlled random search procedure for circuit optimization. The optimization algorithms, problem formulation, and user interaction are discussed, and experimental results are given. >

An envelope-following method for the efficient transient simulation of switching power and filter circuits

Abstract: The transient behavior of circuits like switching power converters and switched capacitor filters are expensive to simulate because they are clocked at a frequency whose period is orders of magnitude smaller than the time interval of interest to the designer. It is possible to reduce the simulation time without compromising accuracy by exploiting the fact that the behavior of such a circuit in a given high-frequency clock cycle is similar, but not identical, to its behavior in the preceding and following cycles. In particular, the envelope of the high-frequency clock can be followed by accurately computing the circuit behavior over occasional cycles. The authors describe the implementation of an envelope-following method that is particularly efficient for switching power and filter circuits, and they present results demonstrating the method's effectiveness. >

Synthesis and optimization procedures for fully and easily testable sequential machines

Abstract: A synthesis procedure is described that produces an optimized fully and easily testable logic implementation of a sequential machine from a state transition graph description of the machine. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic. No access to the memory elements is required. The test sequences for these faults can be obtained using combinational test generation techniques alone. It is shown that an intimate relationship exists between state assignment and the testability of a sequential machine. A technique is also presented of don't-care minimization and added observability which ensures fully testable machines. >

Boolean decomposition in multi-level logic optimization

Abstract: Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic network. Given a two-level logic function, a subset of inputs to the function is selected such that the number of good Boolean factors contained in this subset of inputs is large. If the targeted implementation is a set of interconnected PLAs, the different cube combinations given by the subset of inputs are re-encoded to reduce the number of product terms in the logic function. A novel algorithm for the re-encoding is given that is based on the notion of partial satisfaction of constraints. Algorithms have been developed that identify a set of factors which maximally decrease the literal count of the logic network when they are used as strong divisors. Results obtained on several benchmark examples that illustrate the efficacy of the techniques are presented. >

Optimal logic synthesis and testability: two faces of the same coin

Abstract: The relationships between test generation and logic minimization are described. An overview of the state of the art in combinational and sequential logic synthesis is provided. Combinational logic synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination logic can be obtained as a by-product of the logic minimization step. Equally intimate relationships between the problems of sequential logic synthesis and sequential test generation are envisioned. A recently developed synthesis technique of constrained state assignment and logic optimization which ensures fully testable sequential machines is described briefly. >

Three-dimensional capacitance evaluation on a Connection Machine

Abstract: An algorithm for three-dimensional capacitance evaluation suitable for parallel computers is proposed, and its implementation on a massively parallel architecture, the Connection Machine, is described. After a brief overview of the architecture and the programming style of the Connection Machine is given, a mathematical formulation of the general problem (i.e. the numerical solution of Laplace's equation in three dimensions) is reviewed. The numerical discretization scheme is described along with its implementation on a Connection Machine and the numerical performances of a set of examples are discussed. Experimental results show that this approach allows a fast and efficient solution for this type of problem. >

Techniques for multilayer channel routing

Abstract: The techniques described have been implemented in a multilayer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problems into two-layer and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2 (see ibid., vol.CAD-4, no.3, p.208-19, 1985). In particular, a three-dimensional maze router is used for the vertical connections; this methodology is effective even when cycle constraints are present. Chameleon has produced optimal results on a wide range of industrial and academic examples for a variety of layer and pitch combinations, and can handle a variety of technology constraints. >

ThunderBird: a complete standard cell layout package

Abstract: The generalized standard cell layout style handled by ThunderBird is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. The standard cells are permitted to have varying heights. The two key components of ThunderBird are TimberWolf3.2, a standard cell placement and global routing package, and the YACR II channel router. The placement and global routing proceed over three distinct stages: (1) cell placement for minimum interconnect length, (2) insertion of feedthrough cells or location of built-in feeds, and another interconnect-length minimization; and (3) local changes in placement to reduce the number of wiring tracks required. This channel router features a 100% routing completion rate while usually routing each channel using a number of tracks equal to a density of the channel. Results on industrial circuits versus numerous automatic and manual layout methods showed that ThunderBird yielded area savings ranging from 15 to 75%. >

A modified approach to two-level logic minimization

Abstract: A methodology in which it is not necessary to compute the entire offset is presented, that still provides a global picture. This scheme has been implemented in ESPRESSO with an interface to the multilevel minimization environment MIS. Initial results show that for functions for which the ratio of the size of the cover to the size of the don't care set is small, the new approach is much faster. The initial interest was to use this mainly in a multilevel logic synthesis system where the desired don't care sets are typically large. Some results in this environment are given, and the new scheme is compared with ESPRESSO. >

Finding the steady-state response of analog and microwave circuits

Abstract: The authors present two methods that are capable of computing the steady-state response of a circuit directly: harmonic balance, which is a frequency-domain method, and the finite-difference method, which is based in the time domain. Both of these methods are suitable for use on nonlinear circuits that contain distributed devices and that exhibit either periodic or quasiperiodic steady-state solutions. >

MulCh: a multi-layer channel router using one, two, and three layer partitions

Abstract: Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels with any number of layers and automatically chooses a good assignment of wiring strategies to the different layers. In test cases, MulCh shows significant improvement over Chameleon in terms of channel width, net length, and number of vias. >

A mixed frequency-time approach for finding the steady-state solution of clocked analog circuits

Abstract: Performing detailed simulation of clocked analog circuits (e.g. switched-capacitor filters and switching power supplies) with circuit simulation programs like SPICE is computationally very expensive. The authors present a more efficient method for computing the detailed steady-state solution of clocked analog circuits. The method exploits the property of such circuits that the waveforms in each clock cycle are similar but not exact duplicates of the proceeding or following cycles. Therefore, by computing accurately a few selected cycles, the entire steady-state solution can be constructed efficiently. >

A mixed frequency-time approach for finding the steady-state solution of clocked analog circuits

Abstract: Performing detailed simulation of clocked analog circuits (e.g. switched-capacitor filters and switching power supplies) with circuit simulation programs like SPICE is computationally very expensive. The authors present a more efficient method for computing the detailed steady-state solution of clocked analog circuits. The method exploits the property of such circuits that the waveforms in each clock cycle are similar but not exact duplicates of the proceeding or following cycles. Therefore, by computing accurately a few selected cycles, the entire steady-state solution can be constructed efficiently. >

A band relaxation algorithm for reliable and parallelizable circuit simulation

Abstract: A variable-band relaxation algorithm for solving large linear systems is developed as an alternative to Gauss-Jacobi relaxation. This algorithm seeks to improve the reliability of Gauss-Jacobi relaxation by extracting a variable-sized band from the matrix and solving that band directly. This leads to a relaxation algorithm with provably better convergence properties. The algorithm can be used effectively on a massively parallel computer because band matrices can be solved in log(n) time on n/2 processors. Test results are presented which compare the convergence properties of variable-band and Gauss-Jacobi relaxation. >

Logic Verification, Testing and their Relationship to Logic Synthesis

Abstract: Much work has gone into automating the integrated circuit (IC) design process over the past few years (e.g. [1] [2] [3]). A variety of Computer-Aided Design (CAD) tools for the logic [4] [5] and physical design [6] of integrated circuits have been developed. It is clear that an integrated set of computer design aids coupled with an unified approach to data management is essential for VLSI design. To this end, research has focused on IC synthesis systems [7] i.e. systems which can automatically generate functionally correct mask-level layout of integrated circuit chips from high level, programming language-like specifications.