Showing papers by "Alberto Sangiovanni-Vincentelli published in 1990"

Steady-state methods for simulating analog and microwave circuits

Abstract: 1. Introduction.- 2. Motivation.- 3. Background.- 4. Time-Domain Methods.- 5. Harmonic Balance Theory.- 6. Implementing Harmonic Balance.- 7. Mixed Frequency-Time Method.- 8. Comparisons.- 9. Summary.- Appendix A. Nomenclature.- Appendix B. APFT Time-Point Selection.- 1. Matrix Formulation.- 1.1. Previous Work.- 1.2. Condition Number and Orthonormality.- 1.3. Condition Number and Time-Point Selection.- 1.4. Condition Number and Aliasing.- 2. Near-Orthogonal Selection Algorithm.- 2.1. Time-Point Selection.- 2.2. Constructing the Transform Matrix.- 2.3. APFT Algorithm Results.- Appendix C. Arc-Length Continuation.

Multilevel logic synthesis

Abstract: A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more in-depth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis of the synthesis methods that have become established as practically significant are provided. Also included are some methods that have theoretical interest and potential for future impact. The discussion covers notation and definitions, representation of the network and nodes, logic decomposition/restructuring, logic optimization/minimization, logic synthesis and testing, and technology mapping. >

Implicit state enumeration of finite state machines using BDD's

Abstract: The authors propose a novel method based on transition relations that only requires the ability to compute the BDD (binary decision diagram) for f/sub i/ and outperforms O. Coudert's (1990) algorithm for most examples. The method offers a simple notational framework to express the basic operations used in BDD-based state enumeration algorithms in a unified way and a set of techniques that can speed up range computation dramatically, including a variable ordering heuristic and a method based on transition relations. >

NOVA: state assignment of finite state machines for optimal two-level logic implementation

Abstract: The problem of encoding the states of a synchronous finite state machine (FSM) so that the area of a two-level implementation of the combinational logic is minimized is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible Boolean representation. The authors present algorithms for this solution, based on a novel theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solution have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained. >

Logic synthesis for programmable gate arrays

Abstract: The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures. >

A heuristic algorithm for the fanout problem

Abstract: We present an algorithm to optimally distribute a signal to its required destinations. The choice of the buffers and the topology of the distribution tree depends on the availability of different strength gates and on the load and the required times at the destinations. The general problem is to construct a fanout-tree for a signal so that the required time constraint at the source node is met and the fanout-tree has a minimum area. Since the area constrained fanout problem is NP-complete and area is not a major consideration in present high density designs, we restrict our attention to the simpler problem of designing fast fanout circuits without any area constraint. The proposed algorithm builds the fanout tree by partitioning the fanout signals into subsets and then recursively solving each sub-problem. At each stage the algorithm generates a fanout tree that is an improvement over the previous stage. This feature allows the user to specify the improvement desired by the fanout correction process. The performance of the algorithm, when run on randomly generated distributions of required times and on real design examples, is very promising.

Optimal test set design for analog circuits

Abstract: Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. >

Irredundant sequential machines via optimal logic synthesis

Abstract: It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state transition graph description involves the steps of state minimization, state assignment, and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignments and logic optimization. Here it is shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. Unlike previous synthesis approaches to ensuring fully testable machines, there is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automaton that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements is synthesized. >

Constraint generation for routing analog circuits

Abstract: An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits. >

Constraint-based channel routing for analog and mixed analog/digital circuits

Abstract: A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges, and increasing the weights of edges in the VC graph in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments while attempting to cause minimum increase in the channel height due to the constraints. Use is made of shield nets when necessary. A formal description of the conditions under which the crossover and the adjacency constraints are satisfied is provided and used to construct the appropriate mapping algorithms. The problem of imposing matching constraints on the routing parasitics in a channel with lateral symmetry is addressed. It is observed that perfect matching is not possible for a matched pair of nets with intersecting horizontal spans. A technique to achieve almost perfect mirror symmetry is presented for such pairs of nets. >

Design management based on design traces

Abstract: VOV is an automatic manager for VLSI design. It is based on the idea that CAD tools can leave a trace of their execution. The trace is represented as a bipartite directed and acyclic graph, in which the nodes represent either design data or CAD transactions. By managing and analyzing the traces, VOV offers a wide variety of services related to design management, such as coordination of team design, automatic execution of CAD transactions, and capture of design history and data dependencies. All of these services are provided in a nonintrusive fashion. VOV has the notion of measurement on the design data, an ingredient which is necessary to provide even more services: tracking of design specifications, validation of design data, and design estimation. >

CADICS-cyclic analog-to-digital converter synthesis

Abstract: CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically >

Retiming and resynthesis: optimizing sequential networks with combinational techniques

Abstract: A technique is proposed for optimizing a sequential network by moving the registers to the boundary of the network using an extension of retiming, resynthesizing the combinational logic between the registers using existing logic minimization techniques, and replacing the registers throughout the network using retiming algorithms. A sliding-window optimization technique that considers a large number of different combinational blocks is proposed and demonstrated. The theoretical formulation and results on which the approach is based are given. >

A routing methodology for analog integrated circuits

Abstract: A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described. In this approach, sensitivities of performance to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performance are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated with the parasitics which violated the constraints, and the circuit is rerouted. Results validating the effectiveness of this approach for layout-design automation of analog circuits are reported. >

Computing parametric yield accurately and efficiently

Abstract: An algorithm for computing parametric yield is presented. The algorithm uses statistical modeling techniques and takes advantage of incremental knowledge of the problem to reduce significantly the number of simulations needed. Polynomial regression is used to construct simple equations mapping parameters to measurements. These simple polynomial equations can then replace circuit simulations in the Monte Carlo algorithm for computing parametric yield. The algorithm differs from previous statistical modeling algorithms using polynomial regression for three major reasons: first, the random error that is postulated in polynomial regression equations is taken into account when computing parametric yield; second, the variance of the yield is computed; and third, the algorithm is fully automated. Therefore a direct comparison with Monte Carlo methods can be made. Examples indicate that significant speed-ups can be attained over Monte Carlo methods for a large class of problems. >

Use of performance sensitivities in routing analog circuits

Abstract: The use of performance sensitivities in routing of analog circuits is advocated. Performance constraints are modeled in terms of the sensitivities of performance functions with respect to the routing parasitics for both single-ended and differential circuits. Expressions for the worst-case performance sensitivities due to process variations are derived and shown to play an important role in differential circuits. A well-defined procedure for selecting a set of critical parasitics during layout design is presented. >

MIS-MV: optimization of multi-level logic with multiple-values inputs

Abstract: Techniques are presented for the optimization of multi-level logic with multiple-valued input variables. The motivation for this is to tackle the input encoding problem in logic synthesis, where binary codes need to be found for the different values of a symbolic input variable. Multi-level multiple-valued optimization is used to generate constraints that are used to determine the codes. The state assignment problem in sequential logic synthesis can be approximated as an input encoding problem by ignoring the next state field, which is reasonable when the primary output logic, dominates the next state logic. A novel technique is presented for extracting common factors with multiple-valued variables, and it is shown how other multi-level optimization techniques are easily extended with multiple-valued variables. These ideas have been implemented as algorithms in the MIS-MV program. Practical issues are also presented regarding implementation. Experimental results are also given. >

Performance optimization of pipelined circuits

Abstract: The problem of minimizing the cycle time of a given pipelined circuit is considered. Existing approaches are sub-optimal since they do not consider the possibility of simultaneously resynthesizing the combinational logic and moving the latches using retiming. In the work of S. Malik et al. (Proc. of the Hawaii Inter. Conf. on System Sciences, 1990) the idea of simultaneous retiming and resynthesis was introduced. The authors use the concepts presented in that work to optimize a pipelined circuit to meet a given cycle time. Given an instance of the pipelined performance optimization problem, an instance of a combinational speedup problem is constructed. A constructive proof is given that the pipelined problem has a solution if and only if the combinational problem has a solution. This result is significant since it shows that it is enough to consider only the combinational speedup problem and all known techniques for that domain can be directly applied to generate a solution for the pipelined problem. >

Irredundant sequential machines via optimal logic synthesis

Abstract: It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state-transition-graph description involves the steps of state minimization, state assignment, and logic optimization. It is also shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. There is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automation that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements can be synthesized. These procedures represent an alternative to a scan-design methodology, without the latter's usual area and performance penalty. >

A massively parallel algorithm for three-dimensional device simulation

Abstract: Based on a CGS (conjugate gradient squared) iteration with a partitioned natural ordering, a novel massively parallel algorithm for three-dimensional device simulation is presented. This algorithm requires constant time per matrix iteration independent of the number of grid nodes, and has convergence properties comparable to those of good algorithms currently used on sequential computers. This algorithm has been implemented on the Connection Machine and achieves supercomputer performance for large numbers of grid nodes. Results are presented for a wide variety of devices and mesh sizes. >

'Zone-refining' techniques for IC layout compaction

Abstract: Zone-refining refers to a technique that forms a basis for layout compaction algorithms intermediate between one-dimensional (1-D) compactors and two-dimensional (2-D) placement techniques. An expanded zone in which 2-D refinement techniques are employed is repeatedly swept across the layout in different directions. The basic principle is reviewed and the computational complexity of zone refining is analyzed. The difficulties that had to be overcome in making the basic concept useful for compaction of integrated circuit layouts is discussed. One implementation is described, and some of the tradeoffs made and data structures used to obtain an efficient compactor are examined. The scope of possibilities for other implementations are discussed. >

Extended stuck-fault testability for combinational networks

Abstract: We arguethat a synchronous logic circuit computing a vector boolean function f(x) does so in some time T, and hence the relevant value of the circuit is not its static value (the value at t = oo) but rather its value at t = T. We demonstrate a circuit containing an untestable stuck-at-0 fault with the property that, when the fault is set, the de lay of the circuit increases dramatically, and, hence, the value of the output of the circuit at t = T is incorrect. We show that this fault is not a delay fault in the sense of [5,13,6,12], but is rather a classic stuck fault in the sense of testing theory. This fault is therefore not redun dant byany reasonable definition, even though it is redundant by the conventional definition. We introduce a new concept of redundancy, called r-redundancy. We propose a method of generating tests for r-irredundant stuck faults, and discuss several methods ofobserving these faults. 1 False Paths in Combinational Logic Circuits One issue which arises in the design of integrated circuits is that of ensuring that a design meets a set of timing constraints. Circuit simulators such as SPICE are occasionally used to make this determination; however, circuit simulation is typically too slow to be used for an entire circuit. Hence, a 'Synopsys Incorporated, Mountain View, CA 'This research supported by the Semiconductor Research Corporation under Contract 87-DC-008 Figure 1: A False Path common approach is the use of programs called timing verifiers such as [17] or [10], which areused eitheralone to estimatethe critical delay, or to iden tify the critical path for lateranalysis by a circuit simulator. Timing verifiers are typically quite fast; indeed, for fully-restoring combinational logic the problem is simply that of finding the longest path througha directed acyclic graph, whichis wellknown to be 0(|V|+ \E\). However, these programs will always identify the longest path as the critical path of the circuit. This path, however, is not the path of real interest: the path of interest is the longest path down which a signal can propagate. Paths down which no signal can propagate are called false paths, and the problem of identifying them, and so finding the longest true path through the circuit, is known as the false path problem. Consider, for example, the circuit in figure 1. For x to propagate to a, we must have y = 1. For a to propagate to 6, we must have z 1. But for b to propagate to c, we must have y = z 0. Hence the path {ar,a,6,c,d} is false. The false path problem has been known for some time. The earliest complete discussion in the literature appears to be due to Hrapcenko [9] l. 1Hrapcenko's manuscript was kindly brought to the attention of the authors by Prof. Hrapcenko demonstrated that, for every integer n, there exists a function for which the actual delay of the minimal network is n + 8 but for which the longest path is 2n + 8. Hrapcenko further observed that false paths arise naturally in the design of carry-acceleration adders, and suggested that the longest path through a carry-acceleration adder will be on the order of 2n nodes, while the delay willgrowapproximatelyas n. The problem of detect ing false paths for the purpose of timing verification has been extensively studied over the last few years[4,3,15,14]. A detailed treatment of the phe nomenon and rigorous results can be found in [15], wherein a tight, correct, and robust algorithm to report the longest true path in a network. Hence the delay of a network may be generally assumed to be set to that of the longest sensitizable path. 2 Carry-bypass Adders and r-Irredundant Faults One can picture an arbitrary piece ofsynchronous circuitry as a set of banks of combinational logic separated by clocked registers, as in figure 2. In such a circuit, the clocks may be taken to be set to the length of the longest true path in the preceding bank ofcircuitry; the effective value of the vector boolean function Ci is therefore the values present at the register inputs when the clock

Timing optimization with testability considerations

Abstract: Since redundancy is undesirable in high performance circuits, the authors explore timing optimization procedures to determine whether performance optimization may be achieved without introducing redundancy. They demonstrate the conditions under which timing optimization may introduce single stuck-fault redundancies into a given irredundant circuit and illustrate the difficulties in removing or preventing these redundancies. The authors then resolve the question of whether a testability criterion exists that may be retained or easily maintained as invariant during timing resynthesis. >

Reduced offsets for two-level multi-valued logic minimization

Abstract: The approaches to two-level logic minimization can be classified into two groups: those that use tautology for expansion of cubes and those that use the offset. Tautology based schemes are generally slower and often give somewhat inferior results, because of a limited global picture of the way in which the cube can be expanded. If the offset is used, usually the expansion can be done quickly and in a more global way because it is easier to see effective directions of expansion. The problem with this approach is that there are many functions that have a reasonable size onset and don't care set but the offset is unreasonably large. It was recently shown that for the minimization of such Boolean functions, a new approach using reduced offsets, provides the same global picture and can be computed much faster. In this paper we extend reduced offsets to logic functions with multi-valued inputs.

Harmonic Balance Theory

Abstract: Harmonic balance differs from traditional transient analysis in two fundamental ways. These differences allow harmonic balance to compute periodic and quasiperiodic solutions directly and in certain circumstances give the method significant advantages in terms of accuracy and efficiency. Transient analysis, which uses standard numeric integration, constructs a solution as a collection of time samples with an implied interpolating function. Typically the interpolating function is a low order polynomial. However, polynomials fit sinusoids poorly, and so many points are needed to approximate sinusoidal solutions accurately.

USE OF PERFORMANCE SENSITlVITIES IN ROUTING OF ANALOG CIRCUITS

Abstract: Preliminaries on Routing Use of performance sensitivities in routing of analog circuits is advocated. Performance constraints are modelled in terms of the sensitivities of perfor- mance functions with respect to the routing parasitics for both single-ended and differential circuits. Expressions for the worst-case performance sensi- tivities due to process variations are derived, and shown to play an important role in differential circuits. A well-defined procedure for selecting a set of critical parasitics during layout design is presented.

Time-Domain Methods

Abstract: A very important approach to finding the steady-state response of a system of differential equations is to formulate a boundary-value problem whose solution is the desired steady-state response. Methods for formulating boundary-value problems for periodic solutions was discussed in Chapter 3 and methods for quasiperiodic solutions will be covered in Chapter 7. This chapter presents two important ways of solving these boundary-value problems.