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Showing papers by "Alberto Sangiovanni-Vincentelli published in 1992"


Proceedings ArticleDOI
11 Oct 1992
TL;DR: SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.
Abstract: A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >

551 citations


Proceedings ArticleDOI
01 Jul 1992
TL;DR: A novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit by minimizing the number of states in the corresponding finite-state machine (FSM) and using a critical race-free state assignment technique.
Abstract: The authors propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit They first solve the STG state assignment problem by minimizing the number of states in the corresponding finite-state machine (FSM) and by using a critical race-free state assignment technique State signal transitions may be added to the original STG A lower bound on the number of signals necessary to implement the STG is given The technique significantly increases the applicability of STGs for specifying asynchronous circuits >

69 citations


Proceedings ArticleDOI
03 May 1992
TL;DR: A new constraint-driven methodology for the placeinent of analog IC's is described, where electrical performance specifications are automatically translated into constraints on the layout parasitics and these constraints and the seiisiitivity iiiforinatioii of the circuit are used to control a Simulated Annealingbased placement algorithm.
Abstract: A new constraint-driven methodology for the placeinent of analog IC's is described. Electrical performance specifications are automatically translated into constraints on the layout parasitics. These constraints and the seiisiitivity iiiforinatioii of the circuit are then used to control a Simulated Annealingbased placement algorithm. At each step of the annealing a fast check on performance degradations is performed to guarantee that the tool has the necessary robur,tness.

57 citations


Proceedings ArticleDOI
01 Jul 1992
TL;DR: It is proved that all the robust test vector pairs for any path delay-f fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network.
Abstract: A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique. >

56 citations


Proceedings ArticleDOI
01 Jul 1992
TL;DR: The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures, and present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit.
Abstract: The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use of if-then-else DAGs (directed acyclic graphs) as subject graphs along with BDDs (binary decision diagrams). An important contribution is a very fast algorithm which always gives a match for a function onto the basic block of the architecture, when one exists. Results obtained on a number of benchmark examples are given. >

55 citations


Proceedings ArticleDOI
08 Nov 1992
TL;DR: For performance-driven synthesis of sequential circuits, the optimal clocking problem is considered, and it is shown that it is reducible to a parametric shortest path problem.
Abstract: Performance driven synthesis of sequential circuits relies on techniquessuch as optimal clocking, retiming and resynthesis. In this paper we address the optimal clocking problem and demonstrate that it is reducible to a parametric shortest path problem. We use constraints that take into account both the short and long paths. The main contributions are effrcient graph algorithms to solve the set of constraints necessary for correct clocking.

55 citations


Proceedings ArticleDOI
08 Nov 1992
TL;DR: Both low-level and high-level models for asynchronous circuits and the environment where they operate, together with strong equivalence results between the properties at the low levels, are described and the precise characterization of classical static and dynamic hazards in terms of the model is described.
Abstract: Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses.

41 citations


Proceedings ArticleDOI
10 May 1992
TL;DR: A behavioral representation for the class of Nyquist rate analog to digital (A/D) converters that captures the nominal behavior, as well as all the statistical variations, is presented and applications include identification of important A/D error sources and efficient computation of the distributions of integral nonlinearity and differential non linearity.
Abstract: The authors present a behavioral representation for the class of Nyquist rate analog to digital (A/D) converters that captures the nominal behavior, as well as all the statistical variations. To describe behavioral effects due to process variations a covariance matrix, Sigma /sub t/ is used. Applications of the model include identification of important A/D error sources, efficient computation of the distributions of integral nonlinearity and differential nonlinearity, signal-to-noise plus distortion ratio and efficient worst case and Monte Carlo system simulations. Parameter extraction results are presented that agree well with actual measurements. >

34 citations


Book ChapterDOI
01 Jul 1992
TL;DR: A method for feature construction and selection that finds a minimal set of conjunctive features that are appropriate to perform the classification task and is able to achieve higher classification accuracy.
Abstract: We present a method for feature construction and selection that finds a minimal set of conjunctive features that are appropriate to perform the classification task For problems where this bias is appropriate, the method outperforms other constructive induction algorithms and is able to achieve higher classification accuracy The application of the method in the search for minimal multi-level boolean expressions is presented and analyzed with the help of some examples

33 citations


Proceedings ArticleDOI
03 May 1992
TL;DR: Behavioral representations for detectors and voltage-controlled oscillators that are independent of circuit architectures are presented and parameter extraction techniques are described.
Abstract: This paper presents behavioral representations for detectors and voltage-controlled oscillators that are independent of circuit architectures. Parameter extraction techniques are described. Finally, parameter extraction for a VCO is demonstrated, and an example PLL constructed using the models is simulated and verified against actual chip measurements.

28 citations


Proceedings ArticleDOI
01 Nov 1992
TL;DR: An algorithm for Boolean matching is developed and is used within a technology mapper as a substitute for tree matching algorithms, which is fast and uses symmetries of the gates in the library to speed up the matching process.
Abstract: A new formulation for finding the existence of a Boolean match between two functions with 'don't cares' is presented. An algorithm for Boolean matching is developed based on this new foundation and is used within a technology mapper as a substitute for tree matching algorithms. The new algorithm is fast and uses symmetries of the gates in the library to speed up the matching process. Local 'don't cares' are computed for each function being mapped in terms of its inputs. To reduce the frequency in which Boolean matching is used, the gates in the library are grouped into classes such that it is sufficient to try to match a function with the class representative. Experimental results show significant improvement in the final area of the mapped circuits. >

Journal ArticleDOI
TL;DR: Techniques for the optimization of multilevel logic with multiple-valued input variable is presented to tackle the input encoding problem in logic synthesis, where binary codes must be found for the different values that a symbolic input variable can take.
Abstract: Techniques for the optimization of multilevel logic with multiple-valued input variable is presented. The motivation for this is to tackle the input encoding problem in logic synthesis, where binary codes must be found for the different values that a symbolic input variable can take. It is shown how the other multilevel optimization techniques are easily extended with multiple-valued variables. These ideas have been implemented as algorithms in the program MIS-MV. The practical issues involved in the implementation of these ideas are discussed, and results of using MIS-MV for input encoding on benchmark examples presented. >

Proceedings ArticleDOI
08 Nov 1992
TL;DR: In this paper, the authors present an analysis of valid clock rates in wavepipelined circuits using a technique called Timed Boolean Functions, and demonstrate discontinuity and non-monotonicity of the harmonic number H (r) as a+tion of the clock period r.
Abstract: In thispaper, we conskier the problemof clocking wavepipelined circuits. Wavepipelined circuits can operate at a much higher clock rate than conventional pipelined circuits, because its maximum rate is limited only by the path delay difference instead of the maximum path delay, [Cot69]. Current research in this area has focused on minimizing the path delay difference, hence maximizing the achievable clockfrequency. In this paper, we present an analysis of valid clock rates in wavepipelined circuits using a technique called Timed Boolean Functions. We show that the valid intervals for the clock period can be disconnected. Thus, it is insufslcient to only know the minimum valid clock period in guaranteeing proper operation of pipelined circuits. We provide analytic expressions for the valid clock intervals in terms of both topological delay as well as 2-vector longest and shortest delays. Also uncertainties arising from manufacturing are taken into account. We also illustrate some potential dimulties in computing the exact valid clock intervals by demonstrating discontinuity and non-monotonicity of the harmonic number H (r) (the number of valid simultaneous data waves allowed) as a+tion of the clock period r.

Proceedings ArticleDOI
01 Nov 1992
TL;DR: An efficient approach to the symbolic compaction of analog integrated circuits is presented, which allows the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints.
Abstract: An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allow the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints. >

Proceedings ArticleDOI
01 Jul 1992
TL;DR: An algorithm is presented that derives an equivalent irredundant circuit implementation from a given redundant high-performance circuit, with no increase in delay measured using viability analysis, and an efficient implementation is presented.
Abstract: K. Keutzer et al. (see IEEE Trans. on Comput.-Aided Des., vol.10, no.4, p.427-35 (1991)) have presented an algorithm, known as the KMS algorithm, that derives an equivalent irredundant circuit implementation from a given redundant high-performance circuit, with no increase in delay measured using viability analysis. The authors resolve the main bottlenecks in the KMS algorithm, arising due to an iterative loop of timing analysis, gate duplications, and redundancy removal. A circuit structure property based on path lengths is related to testability and delay. Based on this relationship, an efficient implementation of the KMS algorithm is presented. It consists of the transformation of any Boolean network to an equivalent circuit structure on which a single redundancy removal achieves the same effect as the original KMS algorithm. >

Book ChapterDOI
29 Jun 1992
TL;DR: A new verification strategy for timing constrained finite-state systems, called timed L-process, is proposed that can avoid the state space explosion problem for a class of systems.
Abstract: Verification of many properties can be done without regard to the speed of the components of a finite-state system. However, some of the properties can be verified only under certain timing constraints. We propose a new verification strategy for timing constrained finite-state systems. The strategy can avoid the state space explosion problem for a class of systems. A model of such systems, called timed L-process, compatible with the strategy, is also developed.

Proceedings ArticleDOI
01 Jul 1992
TL;DR: The authors extend the abstract notion of temporal behavior to compare arbitrary circuits with arbitrary multiphase clocking schemes and consider the input-output behavior of circuits with respect to time, and outline a model and a formal definition for the temporal behavior.
Abstract: The authors extend the abstract notion of temporal behavior to compare arbitrary circuits with arbitrary multiphase clocking schemes. They consider the input-output behavior of circuits with respect to time. Properties are discussed that remain invariant under certain transformations. Constraints are derived that permit a legal retiming in the case of multiphase sequential circuits with edge triggered and/or transparent latches. For a particular design style an efficient procedure is described to check for temporal equivalence of sequential circuits. A model and a formal definition for the temporal behavior of an arbitrary multiphase circuits and an algorithm for formal verification of the temporal behavior of circuits are outlined. >

Proceedings ArticleDOI
11 Oct 1992
TL;DR: Experimental results indicate that the improvements obtained are well worth the added complexity of linear program solution.
Abstract: It is shown that hazards can be optimally eliminated from circuits synthesized starting with a signal transition graph (STG) specification. The proposed approach is based on a linear programming (or integer linear programming) formulation, and as such it can be solved efficiently and optimally for a variety of cost functions. Suggested cost functions optimize either the total padded delay, an estimate of the increase in area, or the maximum cycle time of the complete system. It is also shown that delay padding on all fanouts of STG signals is a necessary and sufficient condition for hazard elimination if the structure and delay of each combinational logic block cannot be changed. Experimental results indicate that the improvements obtained are well worth the added complexity of linear program solution. >

Proceedings ArticleDOI
08 Nov 1992
TL;DR: A method for reducing the complexity of CTL model checking on a system of interacting finite state machines is described and the approach is assessed on real-world examples, and the method is demonstrated on a circuit.
Abstract: We describe a method for reducing the complexity of CTL model checking on a system of interactingfinite state machines. The method consists essentially of reducing each component machine with respect to the property we want to verify. and then verifying the property on the composition of the reduced components. The procedure is fully automatic andproduces an exact result. We assess the potential of our approach on real-world examples, and demonstrate the method on a circuit.

Book ChapterDOI
29 Jun 1992
TL;DR: A method for reducing the complexity of temporal logic model checking of a system of interacting finite state machines is described, and it is proved that it yields correct results.
Abstract: We describe a method for reducing the complexity of temporal logic model checking of a system of interacting finite state machines, and prove that it yields correct results. The method consists essentially of reducing each component machine with respect to the property we want to verify, and then verifying the property on the composition of the reduced components. We demonstrate the method on a simple example. We assess the potential of our approach on real-world examples.

Proceedings ArticleDOI
16 Mar 1992
TL;DR: The authors describe the set-up of the generic behavioral models for this simulator, which describe the functional behavior of the analog blocks, independent of the internal architecture, and include the important second-order effects as well as the statistical variations of most parameters.
Abstract: A behavioral simulator is shown to be an essential part of a performance-driven hierarchical top-down design strategy for analog blocks within mixed-signal integrated systems. It is used to accurately estimate the performance of the system while down-mapping the specifications over the hierarchy, in order to avoid time-consuming design iterations. It is also indispensable for the final bottom-up verification after completion of the design, as well as for testing purposes. The authors describe the set-up of the generic behavioral models for this simulator, which describe the functional behavior of the analog blocks, independent of the internal architecture. In addition to the nominal behavior, the models also include the important second-order effects (nonidealities, noise, distortion . . .) as well as the statistical variations of most parameters. This is then illustrated in detail for the statistical minimum-rank model of a Nyquist-rate A/D converter. System-level applications show the effectiveness and accuracy of this model. >

Proceedings ArticleDOI
01 Nov 1992
TL;DR: The problem of partitioning, or decomposing a combinational logic specification is addressed, which operates on the logic specification before the synthesis and mapping steps have been performed, to minimize the number of pins needed to implement the resulting partitions.
Abstract: The problem of partitioning, or decomposing a combinational logic specification is addressed. This method operates on the logic specification before the synthesis and mapping steps have been performed. This allows good circuit decomposition and the logic as needed. The main goal of the algorithm is to minimize the number of pins needed to implement the resulting partitions. This is accomplished by adding logic to reduce the number of pins, and by minimizing the number of pins required for inter-partition communication by encoding the signals that flow between partitions. Algorithms are implemented by the use of binary decision diagrams. >

Book ChapterDOI
31 Aug 1992
TL;DR: The use of programmable devices spans rapid prototyping and dynamically reconfigurable systems and the market is projected to raise rapidly to levels that make this type of devices very appealing for merchant IC manufacturers.
Abstract: User programmable devices are becoming more and more important for system design because of their flexibility that allows much shorter design time and hence better time-to-market. The use of programmable devices spans rapid prototyping and dynamically reconfigurable systems. The market is projected to raise rapidly to levels that make this type of devices very appealing for merchant IC manufacturers. Some of the issues related to the future of these devices as well as to the future of system design methodologies are presented.

Proceedings ArticleDOI
01 Jun 1992
TL;DR: Two algorithms for mapping a sequential circuit onto a specific table look up architecture, namely the Xilinx 3090 architecture, are presented, using the combinational synthesis techniques to solve the sequential synthesis problem.
Abstract: The algorithms for synthesis onto programmable gate arrays (PGAs) have so far addressed only the combinational logic problem. The authors present two algorithms for mapping a sequential circuit onto a specific table look up architecture, namely the Xilinx 3090 architecture. The first algorithm maps combinational and sequential elements simultaneously. In the second, combinational elements are mapped first, followed by the sequential elements. The combinational synthesis techniques are used to solve the sequential synthesis problem. >

Proceedings ArticleDOI
08 Nov 1992
TL;DR: A direct noise analysis approach for mixed-mode systems is presented with experimental results compared with results from the traditional Monte Carlo approach, and it is shown that very low order moments are sufficient for a good estimate of noise effects.
Abstract: In this paper a “direct” noise analysis approach for mixedmode systems is presented with experimental results compared with results from the traditional Monte Carlo approach. The direct approach computes noise effects by performing arithmetic on moments of distribution functions that characterize electronic noise. One key advantage of this approach is its ability to compute low error probabilities. From experimental results, it is shown that very low order moments, such as secondorder, are sufficient for a good estimate of noise effects.

Proceedings ArticleDOI
10 May 1992
TL;DR: A performance-driven analog-to-digital converter (ADC) module generator, CADICS, which generates ADC netlists and layouts from a set of specifications is presented.
Abstract: A performance-driven analog-to-digital converter (ADC) module generator, CADICS, which generates ADC netlists and layouts from a set of specifications is presented. The module generator consists of a circuit synthesis which is based on a hierarchical optimization approach and a layout synthesis which was implemented using a hierarchical layout procedure. At each level of performance, silicon area and power dissipation are optimized so that they are comparable with manual design. The synthesis is built around a one-bit-per-cycle algorithmic A/D converter architecture. Layouts of 6-b, 8-b, and 10-b ADCs generated by CADICS in a 2- mu m CMOS process are shown. >