Showing papers by "Alberto Sangiovanni-Vincentelli published in 1993"

Architecture of field-programmable gate arrays

Abstract: A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed. >

Algorithms for Synthesis and Testing of Asynchronous Circuits

Abstract: From the Publisher: The design of asynchronous circuits is increasingly important in solving problems such as complexity management, modularity, power consumption and clock distribution in large digital integrated circuits. Algorithms for Synthesis and Testing of Asynchronous Circuits describes a variety of mathematical models and algorithms that form the backbone and the body of a new design methodology for asynchronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in exploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design. Algorithms for Synthesis and Testing of Asynchronous Circuits also includes an extensive literature review. The review summarizes and compares classical papers from the 1960s with the most recent developments in the areas of asynchronous circuit design testing and verification.

Minimum padding to satisfy short path constraints

Abstract: Combinational circuits are often embedded in synchronous designs with memory elements at the input and output ports. A performance metric for a circuit is the cycle time of the clock signal. Correct circuit operation requires that all paths have a delay that lies between an upper bound and a lower bound. Traditional approaches in delay optimization for combinational circuits have dealt with methods to decrease the delay of the longest path. We address the issue of satisfying the lower bound constraints. Such a problem also arises in wave pipelining of circuits. We propose to handle short path constraints as a post processing step after traditional delay optimization techniques. There are two issues presented in this paper. We first discuss necessary and sufficient conditions for successful delay insertion without increasing delays of any long paths. In the second part, we present a naive approach to padding delays (greedy heuristic) and an algorithm based on linear programming. We describe an application of the theory to wave pipelining of circuits. Results are presented on a set of benchmark circuits, using two delay models.

An Iterative Approach to Language Containment

Abstract: We propose an iterative approach to formal verification by language containment. We start with some initial abstraction and then iteratively refine it, guided by the failure report from the verification tool. We show that the procedure will terminate, propose a series of heuristic aimed at reducing the size of BDD's used in the computation, and formulate several open problems that could improve efficiency of the procedure. Finally, we present and discuss some initial experimental results.

Delay Fault Coverage and Performance Tradeoffs

Abstract: The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, all known analysis and synthesis techniques for 100% path delay fault testability are infeasible on most circuits. In this paper, we show that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it; hence these delay faults need not be considered in delay fault testing. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed can be selected such that 100% robust delay fault coverage is achieved.

A Formal Specification Model for Hardware/Software Codesign

Abstract: Embedded controllers for reactive real-time applications are implemented as mixed software-hardware systems in this paper we present a model for specification, partitioning, and implementation of such systems The model, called Codesign Finite State Machines (CFSMs), is based on FSMs and is particularly suited to a specific class of systems with relatively low algorithmic complexity Pre-existing formal specification languages can be used by the designer to specify the intended behavior of the system and mapped into our model CFSMs use a non-zero unbounded reaction delay model and hence can be indifferently implemented either in hardware or in software The implementation only restricts the range of variation of some previously undefined delays, thus preserving formal properties of the specification across implementation refinements The communication primitive event broadcasting, is low-level enough to be implemented efficiently and yet general enough to allow higher-level mechanisms (such as channels) to be defined by the designer

Delay Models and Exact Timing Analysis

Abstract: We consider anew the false path problem in timing verification. We argue that any solution to the false path problem inherently incorporates a delay model, and the answer is given in the context of this model. We make explicit the delay model underlying both the “floating” and “transition” sensitization computations, and give the basic assumption underying gate sensitization. We extend sensitization 88theory for the delay model underlying the ”floating mode“ computation to general (complex, possibly asymmetric) gates. This leads to the ability to compute the exact delay of a circuit under the given delay model. We give a new delay model and sensitization computation for ”transition mode“ under a bounded delay model and show that for every bounded delay model there is a natural time quantum such that on each integer-multiple bounded interval of the quantum every signal is a constant. Algorithms for exact delay computation for both floating mode and transition mode delay are given. An implementation for the floating mode model yields practical results on large benchmark circuits.

Dynamic variable reordering for BDD minimization

Abstract: Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested. >

Synthesis methods for field programmable gate arrays

Abstract: Field programmable gate arrays (FPGA ’s) reduce the turnaround time of application-spec@c integrated circuits from weeks to minutes. However, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaround advantage. Consequently, effective design automation tools are needed to reduce design time. Among the most important is logic synthesis. While standard synthesis techniques could be used for FPGA’s, the quality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures. The paper surveys this work. The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays. The emphasis is on tools which attempt to minimize the area of the combinational logic part of a design since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs.

Area routing for analog layout

Abstract: An area router specifically tailored for the layout of analog circuits is presented. It is based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable cost function based on a set of user-defined weights. The weights can be automatically defined based on high-level electrical performance specifications and determine the net scheduling. An algorithm for symmetric routing preserves symmetries in differential architectures. Different current paths can be dealt with in each wire by means of a net partitioning procedure driven by information on the current driven by terminals. Shields can be built between critically coupled wires, in order to guarantee an effective limitation of cross-coupling. The weight-driven programmable cost function makes this router particularly suitable for a performance-driven approach to analog routing. Automatic weight definition also makes the use of the tool independent of the user's expertise. The implemented algorithms are described, and results proving the effectiveness of this approach are given. >

Generalized constraint generation for analog circuit design

Abstract: A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information.

Synthesis method for field programmable gate arrays

Abstract: Logic synthesis algorithms and methods for field-programmable gate arrays (FPGAs) are reviewed. The three most popular types of FPGA architectures are considered, namely, those using logic blocks based on lookup-tables, multiplexers, and wide AND/OR arrays, respectively. The emphasis is on tools that attempt to minimize the area of the combinational logic part of a design, since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs. >

Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits

Abstract: A design methodology for the physical design of analog circuits is proposed. The methodology is based on the automatic generation of constraints on parasitics introduced during the layout phase from constraints on the functional performance of the circuit. In this novel performance-constrained approach, the parasitic constraints drive the layout tools to reduce the need for further layout iterations. Parasitic constraint generation involves (1) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the layout tools while meeting the performance constraints; and (2) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. The constraint generator PARCAR is described and results presented for test circuits. >

Learning Complex Boolean Functions: Algorithms and Applications

Abstract: The most commonly used neural network models are not well suited to direct digital implementations because each node needs to perform a large number of operations between floating point values. Fortunately, the ability to learn from examples and to generalize is not restricted to networks of this type. Indeed, networks where each node implements a simple Boolean function (Boolean networks) can be designed in such a way as to exhibit similar properties. Two algorithms that generate Boolean networks from examples are presented. The results show that these algorithms generalize very well in a class of problems that accept compact Boolean network descriptions. The techniques described are general and can be applied to tasks that are not known to have that characteristic. Two examples of applications are presented: image reconstruction and hand-written character recognition.

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions

Abstract: We propose a general circuit delay model that unifies all previous delay models, e.g. floating, viability, and transition delays, and models introduced in this paper, e.g. delays by sequences of vectors and minimum delays. Then, we formulate the computation of the exact circuit delays, under both bounded and unbounded gate delay models, as a mixed Boolean linear programming using a new formulation technique, called Timed Boolean Function. Next, we compute the exact delays of combinational circuits for transition delay and delay by sequences of vectors. We show that delays by sequences of vectors and floating (or viability) delays are invariant under both bounded and unbounded gate delay models. Finally, we address the effect of gate delay lower bounds on delays of circuits. We demonstrate the effectiveness of the method by giving exact delay results for all ISCAS benchmark circuits (except C6188).

Automated design management using traces

Abstract: An automatic management system for CAD based on the idea that CAD tools can leave a trace of their execution is proposed. The trace, represented as a bipartite directed and acyclic graph in which the nodes represent either design data or tool invocations, is both a record of the design activity and a graph representing the dependencies among the design objects. The architecture of the proposed system is distributed. A server manages the trace, while a number of clients can concurrently interact with the trace through the server. The system is nonintrusive, because it does not affect the way designers interact with the tools. The design manager has been implemented in a system called VOV, which has been tested. >

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis

Abstract: The problem of minimizing the cycle time of a given pipelined circuit is considered. The idea of simultaneous retiming and resynthesis is used to optimize a pipelined circuit to meet a given cycle time. An instance of the pipelined cycle optimization problem is specified by the circuit, a set of input arrival times relative to the clock, a set of required output times relative to the clock, and a given cycle time that it must meet. Given the instance of the pipelined performance optimization problem, the authors construct an instance of a combinational speedup problem. This is specified by a combinational logic circuit, a set of arrival times on the inputs, and a set of required times for the outputs which must be met. A constructive proof that the pipelined problem has a solution if and only if the combinational problem has a solution is given. This result shows that it is enough to consider only the combinational speedup problem, and all known techniques for that can be directly applied to generate a solution for the pipelined problem. >

Performance-driven compaction for analog integrated circuits

Abstract: The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.

A New Exact Minimizer for Two-Level Logic Synthesis

Abstract: We present a new algorithm for exact two-level logic optimization. It differs from the classical approach; rather than generating the set of all prime implicants of a function, and then deriving a covering problem, we derive the covering problem directly and implicitly, and then generate only those primes involved in the covering problem. We represent a set of primes by the cube of their intersection. We then derive some properties of the sets of primes which form this set covering problem. We prove that the set of sets of primes which forms the covering problem for an incompletely-specified logic function.F. is unique. Hence the corresponding set of cubes forms a minimum canonical cover for F. We give a successive reduction algorithm for finding the minimum canonical cover from any initial cover. Using the minimum canonical cover, we then generate only those primes involved in at least one minimal cover of F. We discuss two related heuristic minimization procedures; a relaxed form of the exact procedure, and then an improved form of the ESPRESSO-II procedure. We give experimental results for the exact minimizer. The method is effective; solutions for 10 of the 20 hard examples in the ESPRESSO benchmark set are derived and proved minimum. In addition, for 5 of the remaining examples the minimum canonical cover is derived, but the covering problem remains to be solved exactly.

INDEX: an inductance extractor for superconducting circuits

Abstract: The authors present an extractor, INDEX, designed to extract superconducting circuits from layout. The inductances of the superconducting lines are calculated by a set of analytical models. These self- and mutual-inductance models are generated from a series of numerical simulations and a linear programming curve-fitting. INDEX is based on the MAGIC layout system. INDEX has been tested on a number of cases with good results. A two-junction superconducting quantum interference device (SQUID) was used as one test case. >

Resynthesis of Multi-Phase Pipelines

Abstract: This paper describes an algorithm for deriving necessary and sufficient constraints for a multi-phase sequential pipeline to operate at a target clock cycle. Constraints on delays of the pipeline stages are used to drive a combinational logic delay optimizer to resynthesize the pipeline stages for improved performance. A main advantage of such an approach is that a global picture of the distribution of delays in the circuit is obtained. It also permits safe cycle stealing through level-sensitive latches across pipeline stages.

Analog System Verification in the Presence of Parasitics Using Behavioral Simulation

Abstract: In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster.

Two-level minimization of multivalued functions with large offsets

Abstract: Extends the theory of reduced offsets to logic functions with multivalued inputs. The authors show that the use of multivalued reduced offsets provides the same flexibility that is available with the use of the offset. Offset-based minimization of multivalued functions with large offsets often takes long computation time and requires very large memory and sometimes is not possible within reasonable time and memory. Such functions can be minimized effectively using reduced offsets. >

An algorithm for improving partitions of pin-limited multi-chip systems

Abstract: We present a method for improving a topological partition of a logic circuit. Circuits are partitioned so that they may be implemented by a number of modules (for example, by a number of chips). By reducing the number of I/O pins necessary for communication between the modules we reduce the size of the chips needed to implement the modules, and thereby may also reduce the number of chips needed to implement the modules. Interpartition communication is organized into many unidirectional channels connecting the blocks. The number of lines necessary for implementing a communication channel is reduced by minimizing the amount of information that the channel must transmit, and by encoding the information that is transmitted. The reduction in the channel size usually is accompanied by an increase in the amount of logic in the partition modules. Thus this method is most effectively applied to design styles that are pin-limited; i.e. design styles that have a high ratio of logic area to number of input/output ports. We apply this method to a number of example communication channels and show large reductions in the size of the channels. We also show examples of designs that have fewer chips, or designs have smaller chips after application of these methods.

Synthesis methods for field programmable gate arrays : Field programmable gate arrays

Abstract: Field programmable gate arrays (FPGA's) reduce the turn-around time of application-specific integrated circuits from weeks to minutes. However, the high complexis of their architectures makes manual mapping of designs time consuming and error prone thereby off setting any turnaround advantage. Consequently, effective design automation tools are needed to reduce design time. Among the most important is logic synthesis. While standard synthesis techniques could be used for FPGA's, the quality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures

Some results on the complexity of Boolean functions for table look up architectures

Abstract: We address the problem of determining the "complexity" of Boolean functions where complexity is measured as the minimum number of table look up blocks (TLUs) needed to implement a function. We present three new results. The first shows the exact value of the complexity of the class of (m+1)-input functions in terms of the TLUs with m inputs (m/spl ges/2). The next two derive upper bounds on the complexity, given some information about the representation of the function. One bound needs the number of literals and the number of cubes in a sum-of-products representation, and the other, the number of literals in a factored form. We compare these bounds with the results obtained by a TLU synthesis tool. On average, the factored form bounds are about 20% higher than the synthesized results, and hence are reasonable predictors of the number of TLUs needed. This prediction capability can be employed to quickly estimate, without performing any technology mapping, if a circuit can fit on one chip. >

Architecture of field-programmable gate arrays : Field programmable gate arrays

Abstract: A survey of Field-Programmable Gate Array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size, parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed and several logic blocks used in commercially available FPGA's are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model

The Synthesis Methodology

Abstract: This chapter describes a synthesis procedure that transforms a correct Signal Transition Graph specification withComplete State Codinginto a logic circuit implementing it. The implementation can be shown to be hazard-free, using thebounded wiredelay model if: the circuit operates in an environment that obeys the STG specification, and the bounds on the delays are met by the circuit after manufacture.

A Verification Technique for Gated Clock

Abstract: We present a new model for circuits which have memory elements using conditional clocking. This is termed as the "gated" clock problem. Conventionally most of the recent efforts in timing analysis focus on memory elements controlled by clock signals only. We describe a simple restriction on the conditional signals which makes automatic verification easy. An algorithm to solve the timing verification problem for the case of restricted circuits based on previous approaches is given.