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Showing papers by "Alberto Sangiovanni-Vincentelli published in 2001"


Journal ArticleDOI
TL;DR: The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components to design large digital integrated circuits by using deep submicrometer technologies.
Abstract: The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.

435 citations


Journal ArticleDOI
TL;DR: The authors' vision for the future of embedded-system design involves two essential components: a rigorous methodology for embedded software development and platform-based design.
Abstract: Embedded products have become so complex and must be developed so quickly that current design methodologies are no longer adequate. The authors' vision for the future of embedded-system design involves two essential components: a rigorous methodology for embedded software development and platform-based design.

415 citations


Proceedings ArticleDOI
13 Mar 2001
TL;DR: This work presents a design methodology for PicoRadio Networks, from system conception and optimization to silicon platform implementation, and demonstrates the applicability of the methodology through promising experimental results.
Abstract: One of the most compelling challenges of the next decade is the "last-meter" problem, extending the expanding data network into end-user data-collection and monitoring devices. PicoRadio supports the assembly of an ad hoc wireless network of self-contained mesoscale, low-cost, low-energy sensor and monitor nodes. While technology advances have made it conceivable to deploy wireless networks of heterogeneous nodes, the design of a low-power, low-cost, adaptive node in a reduced time to market is still a challenge. We present a design methodology for PicoRadio Networks, from system conception and optimization to silicon platform implementation. For each phase of the design, we demonstrate the applicability of our methodology through promising experimental results.

79 citations


Book
01 Apr 2001
TL;DR: Substrate Noise Analysis and Optimization for IC Design addresses the main problems posed by substrate noise from both an IC and a CAD designer perspective, along with the mechanisms underlying substrate noise generation, injection, and transport as mentioned in this paper.
Abstract: In the past decade, substrate noise has had a constant and significant impact on the design of analog and mixed-signal integrated circuits. Only recently, with advances in chip miniaturization and innovative circuit design, has substrate noise begun to plague fully digital circuits as well. To combat the effects of substrate noise, heavily over-designed structures are generally adopted, thus seriously limiting the advantages of innovative technologies. Substrate Noise: Analysis and Optimization for IC Design addresses the main problems posed by substrate noise from both an IC and a CAD designer perspective. The effects of substrate noise on performance in digital, analog, and mixed-signal circuits are presented, along with the mechanisms underlying noise generation, injection, and transport. Popular solutions to the substrate noise problem and the trade-offs often debated by designers are extensively discussed. Non-traditional approaches as well as semi-automated techniques to combat substrate noise are also addressed. Substrate Noise: Analysis and Optimization for IC Design will be of interest to researchers and professionals interested in signal integrity, as well as to mixed signal and RF designers.

77 citations


Journal ArticleDOI
01 Mar 2001
TL;DR: Limits to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation are explored.
Abstract: As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation.

76 citations


Journal ArticleDOI
TL;DR: The well-known supervisory control problem for discrete-event dynamical systems (DEDSs) formulated in its basic form is shown to be solvable as a strong model matching problem with measurable disturbances and nondeterministic reference model.
Abstract: The problem of model matching for finite state machines (FSMs) consists of finding a controller for a given open-loop system so that the resulting closed-loop system matches a desired input-output behavior. In this paper, a set of model matching problems is addressed: strong model matching (where the reference model and the plant are deterministic FSMs and the initial conditions are fixed), strong model matching with measurable disturbances (where disturbances are present in the plant), and strong model matching with nondeterministic reference model (where any behavior out of those in the reference model has to be matched by the closed-loop system). Necessary and sufficient conditions for the existence of controllers for all these problems are given. A characterization of all feasible control laws is derived and an efficient synthesis procedure is proposed. Further, the well-known supervisory control problem for discrete-event dynamical systems (DEDSs) formulated in its basic form is shown to be solvable as a strong model matching problem with measurable disturbances and nondeterministic reference model.

64 citations


Book
01 Jan 2001
TL;DR: This work validated deep sub-Micron effects in a Network of PLAS using VLSI Layout Fabrics, a novel approach to fabric cell based design that reduces the uncertainty in the design of fabrics.
Abstract: Contents. List of Figures. List of Tables. Preface. Acknowledgments. Introduction Sunil P Khatri. 1. Introduction. 2. Validating Deep Sub-Micron Effects. 3. VLSI Layout Fabrics. 4. Fabric I - Fabric Cell Based Design. 5. Fabric 3 - Network of PLA Based Design. 6. Wire Removal in a Network of PLAS. 7. Conclusions and Future Directions. Appendices. Index.

62 citations


01 Jan 2001
TL;DR: In this article, a methodology is presented for generating compact models of substrate noise injection in complex logic networks, where the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation.
Abstract: A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns is efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and translated into an energy spectrum which accounts for fundamental frequencies as well as glitch energy. Preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.

47 citations


Proceedings ArticleDOI
04 Nov 2001
TL;DR: In this paper, the parallel language equation A/spl square/X/spl sube/C has been studied in the context of modeling delay-insensitive processes and their environments.
Abstract: The problem of designing a component that, combined with a known part of a system, conforms to a given overall specification arises in several applications ranging from logic synthesis to the design of discrete controllers. We cast the problem as solving abstract equations over languages. Language equations can be defined with respect to several language composition operators such as synchronous composition, /spl middot/, and parallel composition, /spl square/; conformity can be checked by language containment. In this paper, we address parallel language equations. Parallel composition arises in the context of modeling delay-insensitive processes and their environments. The parallel composition operator models an exchange protocol by which an input is followed by an output after a finite exchange of internal signals. It abstracts a system with two components with a single message in transit, such that at each instance either the components exchange messages or one of them communicates with its environment, which submits the next external input to the system only after the system has produced an external output in response to the previous input. We study the most general solutions of the language equation A/spl square/X/spl sube/C, and define the language operators needed to express them. Then we specialize such equations to languages associated with important classes of automata used for modeling systems, e.g., regular languages and FSM languages. In particular, for A/spl square/X/spl sube/C, we give algorithms for computing: the largest FSM language solution, the largest complete solution, and the largest solution whose composition with A yields a complete FSM language. We solve also FSM equations under bounded parallel composition. In this paper, we give concrete algorithms for computing such solutions, and state and prove their correctness.

46 citations


Proceedings ArticleDOI
25 Jun 2001
TL;DR: This paper develops a framework for formalizing the relationships between different models of computation and describes how these relationships can be modified for concurrent systems.
Abstract: System level design is complex. One source of this complexity is that systems are often heterogeneous: different models of computation (e.g., dataflow, FSMs) are used to describe different components of a system. Existing formal methods for concurrent systems are typically based on one particular model of computation, so it is difficult to formalize the interaction between heterogeneous components. In this paper, we develop a framework for formalizing the relationships between different models of computation.

44 citations


Proceedings ArticleDOI
04 Nov 2001
TL;DR: It is demonstrated that the scheme significantly enhances the predictability of wire delays, thereby solving the timing closure problem and results also show that the algorithms result in a significant reduction in total circuit delay.
Abstract: Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation, logic synthesis and layout synthesis are iterated until the estimates match. The number of such iterations is becoming larger as technology scales. Timing closure problems occur mainly due to the difficulty in accurately predicting interconnect delay during logic synthesis. In this paper, we present an algorithm that integrates logic synthesis and global placement to address the timing closure problem. We introduce technology independent algorithms as well as technology dependent algorithms. Our technology independent algorithms are based on the notion of "wire-planning". All these algorithms interleave their logic operations with local and incremental/full global placement, in order to maintain a consistent placement while the algorithm is run. We show that by integrating logic synthesis and placement, we avoid the need to predict interconnect delay during logic synthesis. We demonstrate that our scheme significantly enhances the predictability of wire delays, thereby solving the timing closure problem. This is the main result of our paper. Our results also show that our algorithms result in a significant reduction in total circuit delay. In addition, our technology independent algorithms result in a significant circuit area reduction.

Proceedings ArticleDOI
07 Dec 2001
TL;DR: A formalism to express performance constraints at a high level of abstraction that is based on a solid mathematical foundation, to remove any ambiguity in its interpretation, and yet allows quite simple and natural specification of many typical constraints.
Abstract: We are proposing a formalism to express performance constraints at a high level of abstraction. The formalism allows specifying design performance constraints even before all low level details necessary to evaluate them are known. It is based on a solid mathematical foundation, to remove any ambiguity in its interpretation, and yet it allows quite simple and natural specification of many typical constraints. Once the design details are known, the satisfaction of constraints can be checked either by simulation, or by formal techniques like theorem proving, and, in some cases, by automatic model checking.

Proceedings ArticleDOI
22 Jun 2001
TL;DR: An efficient method to model the interior of the conductors in a quasi-static or full-wave integral equation solver is presented and can successfully and efficiently capture skin effects, proximity effects and transmission line resonances.
Abstract: In this paper, we present an efficient method to model the interior of the conductors in a quasi-static or full-wave integral equation solver. We show how interconnect cross-sectional current distributions can be modeled using a small number of conduction modes as basis functions for the discretization of the mixed potential integral equation (MPIE). Two examples are presented to demonstrate the computational attractiveness of our method. In particular, we show how our new approach can successfully and efficiently capture skin effects, proximity effects and transmission line resonances.

ReportDOI
01 Mar 2001
TL;DR: This volume contains the proceedings of the Fourth Workshop on Hybrid systems: Computation and Control (HSCC 2001) held in Rome, Italy on March 28-30, 2001.
Abstract: : This volume contains the proceedings of the Fourth Workshop on Hybrid systems: Computation and Control (HSCC 2001) held in Rome, Italy on March 28-30, 2001. The Workshop on Hybrid Systems attracts researchers from industry and academia interested in modeling, analysis, synthesis, and implementation of dynamic and reactive systems involving both discrete (integer, logical, symbolic) and continuous behaviors. It is a forum for the discussion of the latest developments in all aspects of hybrid systems, including formal models and computational representations, algorithms and heuristics, computational tools, and new challenging applications.

Book
01 Jan 2001
TL;DR: Control as an Embedded Technology, Optimisation of Hybrid Processes and Hybrid Controllers, and Diagnosis of Physical Systems with Hybrid Models Using Parametrized Causality are reviewed.
Abstract: Control as an Embedded Technology.- Optimisation of Hybrid Processes and Hybrid Controllers.- Embedded Software and Systems: Challenges and Approaches.- Hybrid Systems Applications: An Oxymoron?.- Design of Luenberger Observers for a Class of Hybrid Linear Systems.- Hybrid Modeling and Simulation of Biomolecular Networks.- Compositional Refinement for Hierarchical Hybrid Systems.- Optimal Paths in Weighted Timed Automata.- Reach Set Computations Using Real Quantifier Elimination.- On Hybrid Control of Under-Actuated Mechanical Systems.- On the Decidability of the Reachability Problem for Planar Differential Inclusions.- The Substratum of Impulse and Hybrid Control Systems.- Path-Dependent Impulse and Hybrid Systems.- Hybrid Feedback Control for Path Tracking by a Bounded-Curbature Vehicle.- Minimum-Cost Reachability for Priced Time Automata.- A Hybrid Approach to Traction Control.- Optimal Control Using Bisimulations: Implementation.- A Generalized Approach for Analysis and Control of Discrete-Time Piecewise Affine and Hybrid Systems.- Accurate Event Detection for Simulating Hybrid Systems.- A Clustering Technique for the Identification of Piecewise Affine systems.- Lateral Inhibition through Delta-Notch Signaling: A Piecewise Affine Hybrid Model.- Supervision of Event-Driven Hybrid Systems: Modeling and Synthesis.- Control of Piecewise-Linear Hybrid Systems on Simplices and Rectangles.- Assume-Guarantee Reasoning for Hierarchical Hybrid Systems.- Hybrid Modeling of TCP Congestion Control.- Hybrid Geodesics as Optimal Solutions to the Collision-Free Motion Planning Problem.- Nonlinear Adaptive Backstepping with Estimator Resetting Using Multiple Observers.- Mode Switching Synthesis for Reachability Specifications.- Characterization of Stabilizing Switching Sequences in Switched Linear Systems Using Piecewise Linear Lyapunov Functions.- On a Novel Class of Bifurcations in Hybrid Dynamical Systems.- Global Controllability of Hybrid Systems with Controlled and Autonomous Switchings.- Modeling of Continuous-Discrete Processes.- Hybrid I/O Automata Revisited.- Validating a Hamilton-Jacobi Approximation to Hybrid System Reachable Sets.- Robust Controller Synthesis for Hybrid Systems Using Modal Logic.- Diagnosis of Physical Systems with Hybrid Models Using Parametrized Causality.- Addressing Multiobjective Control: Safety and Performance through Constrained Optimization.- Representation of Quantised Systems by the Frobenius-Perron Operator.- Semi-de1cidable Synthesis for Triangular Hybrid Systems.- Hybrid Abstractions that Preserve Timed Languages.

Book ChapterDOI
08 Oct 2001
TL;DR: This paper outlines a framework that is to use for studying the problems of abstraction and refinement in the context of embedded software for hybrid systems.
Abstract: The methodologies that are in use today for software development rely on representations and techniques appropriate for the applications (compilers, business applications, CAD, etc.) that have been traditionally implemented on programmable processors. Embedded software is different: by virtue of being embedded in a surrounding system, the software must be able to continuously react to stimula in the desired way. Verifying the correctness of the system requires that the model of the software be transformed to include (refine) or exclude (abstract) information to retain only what is relevant to the task at hand. In this paper, we outline a framework that we inted to use for studying the problems of abstraction and refinement in the context of embedded software for hybrid systems.

Proceedings ArticleDOI
04 Nov 2001
TL;DR: An analytical approach based on concurrent processes modeled as Stochastic Automata Networks (SANs) that can be effectively used to integrate power and performance metrics in system-level design is introduced.
Abstract: This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on concurrent processes modeled as Stochastic Automata Networks (SANs) that can be effectively used to integrate power and performance metrics in system-level design. We show that 1) under various input traces and wireless channel conditions, the average-case behavior of a multimedia system consisting of a video encoder/decoder pair is characterized by very different probability distributions and power consumption values and 2) in order to identify the best trade-off between power and performance figures, one must take into consideration the entire environment (i.e., encoder, decoder, and channel) for which the system is being designed. Compared to using simulation, our analytical technique reduces the time needed to find the steady-state behavior by orders of magnitude, with some limited loss in accuracy compared to the exact solution. We illustrate the potential of our methodology using the MPEG-2 video as the driver application.

Proceedings ArticleDOI
16 Nov 2001
TL;DR: An optimised, automated, transparent and mathematically correct flow from product specification through to implementation for SW-dominated products implemented with highly programmable platforms is envisaged.
Abstract: In this paper we describe a vision for the future evolution of Embedded SW (ESW) design methodologies as part of overall Embedded Systems (ES) development. Fundamentally, we believe that the way in which embedded SW is developed today must change radically. The key steps are: first, to link embedded software upwards in the abstraction layers to system functionality; and second, to link embedded software to the programmable platforms that support it. This will provide the much-needed means to verify whether the constraints posed on Embedded Systems are met. We envisage an optimised, automated, transparent and mathematically correct flow from product specification through to implementation for SW-dominated products implemented with highly programmable platforms.

Patent
01 May 2001
TL;DR: In this paper, the authors present a method for annotating software with performance information, such as timing information, resource usage information, and hardware simulation model information, using assembler-level source code.
Abstract: Systems and methods are provided for annotating software with performance information. The computer code is compiled into assembler code, the assembler code is translated into a simulation model, expressed in assembler-level source code. The simulation model is annotated with information for calculating various performance parameters of the software, such as timing information, or resource usage information. The simulation model is then re-compiled and executed on a simulator, optionally including a hardware simulation model, and the performance information is computed from the simulation.

Book ChapterDOI
28 Mar 2001
TL;DR: This work provides a single-pass algorithm to solve the dynamic programming problem that arises, with added constraints to ensure non-Zeno trajectories.
Abstract: We consider the synthesis of optimal controls for continuous feedback systems by recasting the problem to a hybrid optimal control problem which is to synthesize optimal enabling conditions for switching between locations in which the control is constant. We provide a single-pass algorithm to solve the dynamic programming problem that arises, with added constraints to ensure non-Zeno trajectories.

Journal ArticleDOI
TL;DR: This work defines synchronous equivalence for embedded systems that strongly resembles the concept of functional equivalenceFor sequential circuits and applies this property to an ATM switch, demonstrating that synchronOUS equivalence opens design exploration avenues uncharted before.
Abstract: Design space exploration is the process of analyzing several functionally equivalent alternatives to determine the most suitable one. A fundamental question is whether an implementation is consistent with the high-level specification or whether two implementations are "equivalent." The synchronous assumption has made it possible to develop efficient procedures for establishing functional equivalence between different implementations in the domains of synchronous circuits and synchronous reactive systems. We extend this notion to embedded systems that do not satisfy the synchronous assumption inside their boundaries but only at the interface with the environment. Leveraging this property, we define synchronous equivalence for embedded systems that strongly resembles the concept of functional equivalence for sequential circuits. We develop efficient synchronous equivalence analysis algorithms for embedded system designs. The efficiency comes from analyzing the behavior statically on abstract representations, at a cost that some of the negative results may be false, i.e. the analysis is conservative. We develop primitives for making the representation more/less abstract, trading off complexity of the algorithms with the conservativeness of the results. We apply our analysis algorithms to an ATM switch and demonstrate that synchronous equivalence opens design exploration avenues uncharted before.

Proceedings ArticleDOI
04 Nov 2001
TL;DR: A mesh analysis approach for computing the discretized currents in both the conductors and the dielectrics is described and it is shown that this fully mesh-based formulation can be cast into a form using provably positive semidefinite matrices, making for easy application of Krylov-subspace based model-reduction schemes to generate accurate guaranteed passive reduced-order models.
Abstract: Interconnect structures including dielectrics can be modeled by an integral equation method using volume currents and surface charges for the conductors, and volume polarization currents and surface charges for the dielectrics. In this paper we describe a mesh analysis approach for computing the discretized currents in both the conductors and the dielectrics. We then show that this fully mesh-based formulation can be cast into a form using provably positive semidefinite matrices, making for easy application of Krylov-subspace based model-reduction schemes to generate accurate guaranteed passive reduced-order models. Several printed circuit board examples are given to demonstrate the effectiveness of the strategy.

Journal ArticleDOI
TL;DR: In this article, the problem of delivering as quickly as possible a requested torque produced by a spark ignition engine equipped with a multi-point port injection manifold and with electronic throttle is solved for a detailed, cycle-accurate hybrid model with a hybrid control approach based on a two-step process.
Abstract: SUMMARY We address the problem of delivering as quickly as possible a requested torque produced by a spark ignition engine equipped with a multi-point port injection manifold and with electronic throttle. The optimal control problem, subject to the constraint that the air}fuel ratio stays within a pre-assigned range around the stoichiometric ratio, is solved for a detailed, cycle-accurate hybrid model with a hybrid control approach based on a two-step process. In the "rst step, a continuous approximation of the hybrid problem is solved exactly. Then, the control law so obtained is adjusted to satisfy the constraints imposed by the hybrid model. The quality of the control law has been in part analytically demonstrated and in part validated with simulations. Copyright 2001 John Wiley & Sons, Ltd.

Proceedings ArticleDOI
04 Dec 2001
TL;DR: A unified framework, the Tagged Signal Model (TSM) is proposed based on an extended theory of hybrid systems that can put together engine models that are a combination of finite state machines, discrete event and sequential processes, powertrain models, sensors and actuators, and at last controller models.
Abstract: In this paper we discuss issues involved in system level design of complex embedded systems, we focus on automotive engine and power-train control applications. We briefly illustrate the problem of capturing a complicated plant and of designing control laws that satisfy multiple requirements in different regions of operation. We propose a unified framework, the Tagged Signal Model (TSM) based on an extended theory of hybrid systems. Our framework can put together engine models that are a combination of finite state machines, discrete event and sequential processes, powertrain models, sensors and actuators, and at last controller models. The synchronous reactive language formalism can be used for the design of the controller so that synthesis procedures can be followed to generate either the hardware or the software.


Proceedings ArticleDOI
30 May 2001
TL;DR: An application of scheduling theory to reactive real-time transactions (task groups) implementing a formal model of this kind, used in the context of the POLIS toolset: a network of extended finite state machines communicating asynchronously.
Abstract: The development of control-dominated embedded systems can be largely automated by making use of formal models of computation. In some of these models functional objects are not independently activated, triggered by time or external events, as in conventional real-time scheduling models, but each communication between any two functional objects carries an activation signal from the sender to the receiver. This paper presents an application of scheduling theory to reactive real-time transactions (task groups) implementing a formal model of this kind, used in the context of the POLIS toolset: a network of extended finite state machines communicating asynchronously. Task instances are activated in response to internal and/or external events and the objective of the scheduling problem is to avoid the loss of events exchanged by the tasks and to minimize the number of task instances activated in response to external events. The paper presents a schedulability analysis, two priority assignment algorithms, and an experimental part with a dashboard controller example.

Book ChapterDOI
28 Mar 2001
TL;DR: Major applications of hybrid systems require a great deal of work both to select the right abstraction level and to derive algo- rithms that exploit the particularities of the domain of application.
Abstract: Hybrid systems are richly expressive models for a large variety of potential ap- plications. However, being so rich as to include continuous nonlinear dynamical systems, discrete-event systems and other models of computation (unite-state machines and data ow come to mind here), they are not amenable to com- putationally attractive techniques for synthesis and analysis and present hard numerical problems to simulation. Hence, applying the methods typical of this technology requires non trivial amount of approximation and abstraction. And approximation and abstraction are effective only if the domain of application is deeply understood. Thus, significant applications of hybrid systems require a great deal of work both to select the right abstraction level and to derive algo- rithms that exploit the particularities of the domain of application. In addition, one needs to motivate and document convincingly why using hybrid systems can yield better results than other techniques. In this respect, there has been an on- going debate as to what constitutes a meaningful result in applications: on one hand, novel languages for describing hybrid systems and capturing their prop- erties may be considered sophomoric exercises by experts in languages, on the other, formal verification tools that in general can handle small systems may be seen as toys for who is trying to tame entire chemical plants. On the simulation front, how to deal with discontinuities of trajectories is a major issue. Numerical analysts have been looking at these problems only recently and with a great deal of skepticism as to what can be proven rigorously. Hybrid system researchers are now getting seriously in the simulation arena exploiting what has been done in the numerical analysis arena.

Proceedings ArticleDOI
04 Dec 2001
TL;DR: Two language extensions for C and Java build upon the ESTEREL synchronous semantic foundation that provides support for waiting, concurrency and preemption, and nicely support specification of mixed control/data modules.
Abstract: We have presented two language extensions for C and Java for embedded system specification, simulation and implementation. The two languages JESTER and ECL build upon the ESTEREL synchronous semantic foundation that provides support for waiting, concurrency and preemption. They nicely support specification of mixed control/data modules. The compilation is performed by splitting the source code into reactive ESTEREL code (as large as possible, in the current implementation) and data-dominated C or Java code. The large reactive portion can be robustly optimized and synthesized to either hardware or software, while the C residual code must be either implemented in software as is or the user must provide a a hardware implementation.

Proceedings ArticleDOI
17 Apr 2001
TL;DR: A new approach to performance analysis of DSP-kernel software, based on high-level abstractions, called implicit cache simulation, which can take into account any kind of instruction cache as well as code allocation effects, and is compared with the trace-driven simulation approach.
Abstract: We introduce a new approach to performance analysis of DSP-kernel software, based on high-level abstractions, called implicit cache simulation. The method can take into account any kind of instruction cache as well as code allocation effects. We show that no loss of estimation accuracy is implied by the proposed abstractions. Moreover the speed of the method is such that it can be efficiently used as a system-level design tool. We compare implicit cache simulation with the trace-driven simulation approach, commonly used in industry. Experimental results show that our method is 4 times faster in the average and up to 11 times faster than trace-driven simulation.