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Alberto Sangiovanni-Vincentelli

Bio: Alberto Sangiovanni-Vincentelli is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic synthesis & Finite-state machine. The author has an hindex of 99, co-authored 934 publications receiving 45201 citations. Previous affiliations of Alberto Sangiovanni-Vincentelli include National University of Singapore & Lawrence Berkeley National Laboratory.


Papers
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Proceedings ArticleDOI
07 Nov 1999
TL;DR: A new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires is proposed as well as a report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.
Abstract: In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionaly equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.

192 citations

Proceedings ArticleDOI
22 Oct 2003
TL;DR: A taxonomy for classification of faults in sensor networks and the first on-line model-based testing technique that can be applied on an arbitrary system of heterogeneous sensors with an arbitrary type of fault model is introduced.
Abstract: On-line fault detection in sensor networks is of paramount importance due to the convergence of a variety of challenging technological, application, conceptual, and safety related factors. We introduce a taxonomy for classification of faults in sensor networks and the first on-line model-based testing technique. The approach is generic in the sense that it can be applied on an arbitrary system of heterogeneous sensors with an arbitrary type of fault model, while it provides a flexible tradeoff between accuracy and latency. The key idea is to formulate on-line testing as a set of instances of a non-linear function minimization and consequently apply nonparametric statistical methods to identify the sensors that have the highest probability to be faulty. The optimization is conducted using the Powell nonlinear function minimization method. The effectiveness of the approach is evaluated in the presence of random noise using a system of light sensors.

191 citations

Journal ArticleDOI
TL;DR: A modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems and experimental results show that the new algorithm obtains results comparable in quality to those of the single processor version.
Abstract: A modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems. The algorithm has been implemented on the Sequent Balance 8000, a multiprocessor system with a shared-memory architecture. Experimental results show that the new algorithm obtains results comparable in quality to those of the single processor version; processor utilization is greater than 80 percent using up to eight processors.

190 citations

Book
30 Nov 1986
TL;DR: This chapter discusses circuit simulation for IC design, the implementation of WR, and the results of the Parallel Algorithm Test Results.
Abstract: 1 - Introduction.- Section 1.1 - Simulation For IC Design.- Section 1.2 - Circuit Simulation.- Section 1.3 - Standard Circuit Simulators.- Section 1.4 - Relaxation-Based Circuit Simulators.- Section 1.5 - Notation.- 2 - The Circuit Simulation Problem.- Section 2.1 - Formulation of the Equations.- Section2.1.1 - Branch Equations.- Section 2.1.2 - KCL and KVL.- Section 2.1.3 - Nodal Analysis.- Section 2.1.4 - Extending The Nodal Analysis Technique.- Section 2.2 - Mathematical Properties of the Equations.- Section 2.2.1 - Existence of Solutions.- Section 2.2.2 - Diagonal Dominance and the Capacitance Matrix.- Section 2.2.3 - Resistor-and-Grounded-Capacitor (RGC) Networks.- Section 2.3 - Numerical Integration Properties.- Section 2.3.1 - Consistency, Stability, and Convergence.- Section 2.3.2 - Stiffness and A-Stability.- Section 2.3.3 - Charge Conservation.- Section 2.3.4 - Domain of Dependence.- 3 - Numerical Techniques.- Section 3.1 - Numerical Integration in General-Purpose Simulators.- Section 3.2 - Properties of Multistep Integration Methods.- Section 3.3 - Relaxation Decomposition.- Section 3.4 - Semi-Implicit Numerical Integration Methods.- Section 3.5 - Relaxation Versus Semi-Implicit Integration.- 4 - Waveform Relaxation.- Section 4.1 - The Basic WR Algorithm.- Section 4.2 - Convergence Proof for the Basic WR Algorithm.- Section 4.3 - Waveform Relaxation-Newton Methods.- Section 4.4 - Nonstationary WR Algorithms.- 5 - Accelerating WR Convergence.- Section 5.1 - Uniformity of WR Convergence.- Section 5.2 - Partitioning Large Systems.- Section 5.3 - Ordering the Equations.- 6 - Discretized WR Algorithms.- Section 6.1 - The Global-Timestep Case.- Section 6.2 - Fixed Global-Timestep WR Convergence Theorem.- Section 6.3 - The Multirate WR Convergence Theorem.- 7 - The Implementation of WR.- Section 7.1 - Partitioning Mos Circuits.- Section 7.2 - Ordering the Subsystem Computation.- Section 7.3 - Computation of the Subsystem Waveforms.- Section 7.4 - Window Size Determination.- Section 7.5 - Partial Waveform Convergence.- Section 7.6 - Experimental Results.- 8 - Parallel WR Algorithms.- Section 8.1 - An Overview of the Shared-Memory Computer.- Section 8.2 - Mixed Seidel/Jacobi Parallel WR Algorithm.- Section 8.3 - Timepoint-Pipelining WR Algorithm.- Section 8.4 - Parallel Algorithm Test Results.- References.

184 citations

Journal ArticleDOI
TL;DR: Algorithms for fault-driven test set selection are presented based on an analysis of the types of tests needed for different types of faults, and a major reduction in testing time should come from reducing the number of specification tests that need to be performed.
Abstract: Analog testing is a difficult task without a clearcut methodology. Analog circuits are tested for satisfying their specifications, not for faults. Given the high cost of testing analog specifications, it is proposed that tests for analog circuits should be designed to detect faults. Therefore analog fault modeling is discussed. Based on an analysis of the types of tests needed for different types of faults, algorithms for fault-driven test set selection are presented. A major reduction in testing time should come from reducing the number of specification tests that need to be performed. Hence algorithms are presented for minimizing specification testing time. After specification testing time is minimized, the resulting test sets are supplemented with some simple, possibly non-specification, tests to achieve 100% fault coverage. Examples indicate that fault-driven test set development can lead to drastic reductions in production testing time. >

182 citations


Cited by
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Journal ArticleDOI
01 Jan 1998
TL;DR: In this article, a graph transformer network (GTN) is proposed for handwritten character recognition, which can be used to synthesize a complex decision surface that can classify high-dimensional patterns, such as handwritten characters.
Abstract: Multilayer neural networks trained with the back-propagation algorithm constitute the best example of a successful gradient based learning technique. Given an appropriate network architecture, gradient-based learning algorithms can be used to synthesize a complex decision surface that can classify high-dimensional patterns, such as handwritten characters, with minimal preprocessing. This paper reviews various methods applied to handwritten character recognition and compares them on a standard handwritten digit recognition task. Convolutional neural networks, which are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques. Real-life document recognition systems are composed of multiple modules including field extraction, segmentation recognition, and language modeling. A new learning paradigm, called graph transformer networks (GTN), allows such multimodule systems to be trained globally using gradient-based methods so as to minimize an overall performance measure. Two systems for online handwriting recognition are described. Experiments demonstrate the advantage of global training, and the flexibility of graph transformer networks. A graph transformer network for reading a bank cheque is also described. It uses convolutional neural network character recognizers combined with global training techniques to provide record accuracy on business and personal cheques. It is deployed commercially and reads several million cheques per day.

42,067 citations

Journal ArticleDOI
Rainer Storn1, Kenneth Price
TL;DR: In this article, a new heuristic approach for minimizing possibly nonlinear and non-differentiable continuous space functions is presented, which requires few control variables, is robust, easy to use, and lends itself very well to parallel computation.
Abstract: A new heuristic approach for minimizing possibly nonlinear and non-differentiable continuous space functions is presented. By means of an extensive testbed it is demonstrated that the new method converges faster and with more certainty than many other acclaimed global optimization methods. The new method requires few control variables, is robust, easy to use, and lends itself very well to parallel computation.

24,053 citations

Journal ArticleDOI
01 Apr 1988-Nature
TL;DR: In this paper, a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) is presented.
Abstract: Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

9,929 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Abstract: In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach.

9,021 citations

Book
25 Apr 2008
TL;DR: Principles of Model Checking offers a comprehensive introduction to model checking that is not only a text suitable for classroom use but also a valuable reference for researchers and practitioners in the field.
Abstract: Our growing dependence on increasingly complex computer and software systems necessitates the development of formalisms, techniques, and tools for assessing functional properties of these systems. One such technique that has emerged in the last twenty years is model checking, which systematically (and automatically) checks whether a model of a given system satisfies a desired property such as deadlock freedom, invariants, and request-response properties. This automated technique for verification and debugging has developed into a mature and widely used approach with many applications. Principles of Model Checking offers a comprehensive introduction to model checking that is not only a text suitable for classroom use but also a valuable reference for researchers and practitioners in the field. The book begins with the basic principles for modeling concurrent and communicating systems, introduces different classes of properties (including safety and liveness), presents the notion of fairness, and provides automata-based algorithms for these properties. It introduces the temporal logics LTL and CTL, compares them, and covers algorithms for verifying these logics, discussing real-time systems as well as systems subject to random phenomena. Separate chapters treat such efficiency-improving techniques as abstraction and symbolic manipulation. The book includes an extensive set of examples (most of which run through several chapters) and a complete set of basic results accompanied by detailed proofs. Each chapter concludes with a summary, bibliographic notes, and an extensive list of exercises of both practical and theoretical nature.

4,905 citations