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Alberto Sangiovanni-Vincentelli
Researcher at University of California, Berkeley
Publications - 946
Citations - 47259
Alberto Sangiovanni-Vincentelli is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic synthesis & Finite-state machine. The author has an hindex of 99, co-authored 934 publications receiving 45201 citations. Previous affiliations of Alberto Sangiovanni-Vincentelli include National University of Singapore & Lawrence Berkeley National Laboratory.
Papers
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Proceedings ArticleDOI
Noise analysis of non-autonomous radio frequency circuits
TL;DR: The output noise of a nonlinear non-autonomous circuit, driven by a periodic input signal with phase noise, is stationary-not cyclostationary (as would be predicted by traditional analyses), and it is shown that effect of the input signal phase noise is to act as additional white noise source.
Journal ArticleDOI
Enhanced methods of feasible directions for engineering design problems
TL;DR: After the advantages of methods of feasible directions in an engineering design environment are pointed out, several modifications to the classical scheme are proposed, aimed at improving computational efficiency while preserving convergence properties.
Proceedings ArticleDOI
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain
Leonardo Mangeruca,Alberto Ferrari,Alberto Sangiovanni-Vincentelli,Andrea Pierantoni,Michele Pennese +4 more
TL;DR: A case study in the design of automotive engine controllers: the development of a knock detection algorithm and its implementation in an optimized platform and the final design with the trade-offs explored.
Journal ArticleDOI
Design Automation for Cyber-Physical Systems [Scanning the Issue]
TL;DR: The cyber components of autonomous vehicles are much more intelligent and complex than those of traditional vehicles, and interact more directly and closely with the physical environment.
Single and multi-cpu performance modeling for embedded systems
TL;DR: An approach for automatically annotating timing information obtained from a cycle-level model back to the original application source code is developed, and the annotated source code can then be simulated without the underlying architecture and still maintain good timing accuracy.