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Alberto Sangiovanni-Vincentelli
Researcher at University of California, Berkeley
Publications - 946
Citations - 47259
Alberto Sangiovanni-Vincentelli is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic synthesis & Finite-state machine. The author has an hindex of 99, co-authored 934 publications receiving 45201 citations. Previous affiliations of Alberto Sangiovanni-Vincentelli include National University of Singapore & Lawrence Berkeley National Laboratory.
Papers
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Proceedings ArticleDOI
A Mixed Discrete-Continuous Optimization Scheme for Cyber-Physical System Architecture Exploration
TL;DR: This work proposes a methodology for architecture exploration for Cyber-Physical Systems (CPS) based on an iterative, optimization-based approach, where a discrete architecture selection engine is placed in a loop with a continuous sizing engine.
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Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions
TL;DR: A general circuit delay model is proposed that unifies all previous delay models, e.g. floating, viability, and transition delays, and shows that delays by sequences of vectors and floating (or viability) delays are invariant under both bounded and unbounded gate delay models.
Proceedings ArticleDOI
Stochastic contracts for cyber-physical system design under probabilistic requirements
TL;DR: An assume-guarantee contract framework for the design of cyber-physical systems, modeled as closed-loop control systems, under probabilistic requirements, using a variant of signal temporal logic, namely, Stochastic Signal Temporal Logic (StSTL), to specify system behaviors as well as contract assumptions and guarantees, thus enabling automatic reasoning about requirements of stochastic systems.
Proceedings ArticleDOI
SERAN: a semi random protocol solution for clustered wireless sensor networks
A. Bonivento,Carlo Fischione,Alberto Sangiovanni-Vincentelli,Fabio Graziosi,Fortunato Santucci +4 more
TL;DR: This work considers a representative case study and presents simulation results to show SERAN efficiency, which is robust against node failures and clock drifts, supports data aggregation algorithms and is easily implementable in any of the existing hardware platforms.
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Schedule validation for embedded reactive real-time systems
TL;DR: A static priority scheme is proposed here that can be formally validated both for preemptive and non-preemptive schedules and is conservative in the sense that a valid schedule may be bedeclared invalid, but no invalid schedule may bedeClared valid.