Alessandra Nardi

Bio: Alessandra Nardi is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Design for manufacturability & Static timing analysis. The author has an hindex of 11, co-authored 18 publications receiving 307 citations. Previous affiliations of Alessandra Nardi include University of California, Berkeley & University of Padua.

Analysis of the impact of process variations on clock skew

Abstract: In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network.

Functional safety methodologies for automotive applications

Abstract: Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies and design tool providers. This paper introduces some basic concepts of functional safety analysis and optimization and shows the bridge with the tradition design flow. Considerations are presented on how design methodologies are capturing and addressing the new safety metrics.

Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep sub-micron CMOS technologies

Abstract: The impact of process fluctuations on the variability of deep sub-micron (DSM) VLSI circuit performances is investigated in this paper. In particular, we show that, as process dimensions scale down in the sub half-micron region, the relative weight of process variability tends to increase, thus wearing down a nonnegligible portion of the benefits that are expected from minimum feature size scaling. Therefore, in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as in the assigned probability technique (APT) (Dal Fabbro et al, Proc. 32nd ACM/IEEE Design Automation Conf., pp. 702-6, 1995). The application of the APT technique to a 16-bit ripple-carry adder designed in 0.35 /spl mu/m, 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies with a power supply ranging from 3.3 V down to 1 V demonstrates how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high performance or low-power systems in 0.18 /spl mu/m and lesser technologies.

Logic synthesis for manufacturability

Abstract: Design optimization during synthesis is for area and/or performance while optimization for yield occurs at the layout level. To obtain abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis. Design for manufacturability denotes all techniques designers use to estimate and control yield and robustness during the design phase, prior to manufacturing.

System-on-Chip Test Architectures: Nanometer Design for Testability

Abstract: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.

Device Modeling for Analog and RF CMOS Circuit Design: Ytterdal/Device

Abstract: Preface. MOSFET Device Physics and Operation. MOSFET Fabrication. RF Modeling. Noise Modeling. Proper Modeling for Accurate Distortion Analysis. The BSIM4 MOSFET Model. The EKV Model. Other MOSFET Models. Bipolar Transistors in CMOS Technologies. Modeling of Passive Devices. Effects and Modeling of Process Variation and Device Mismatch. Quality Assurance of MOSFET Models. Index.

Reducing clock skew variability via cross links

Abstract: Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wire-length. In this paper, we suggest to construct a low cost non-tree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a non-tree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated non-tree delay computation is circumvented. Further, they can be applied to the recently popular non-zero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2 increase of wirelength.

Stochastic analysis of interconnect performance in the presence of process variations

Abstract: Deformations in interconnect due to process variations can lead to significant performance degradation in deep sub-micron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA, results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.

Statistical circuit modeling and optimization

Abstract: This tutorial reviews statistical circuit modeling and optimization and its applications in integrated circuit design. Motivated by a discussion of the importance of statistical design techniques, it introduces the primary concepts and discusses the main techniques used for statistical modeling, analysis and optimization. It also considers some of the important open questions.