Alessandro Vincenzi

Bio: Alessandro Vincenzi is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Computer cooling & Three-dimensional integrated circuit. The author has an hindex of 6, co-authored 10 publications receiving 504 citations.

3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling

Abstract: Three dimensional stacked integrated circuits (3D ICs) are extremely attractive for overcoming the barriers in interconnect scaling, offering an opportunity to continue the CMOS performance trends for the next decade. However, from a thermal perspective, vertical integration of high-performance ICs in the form of 3D stacks is highly demanding since the effective areal heat dissipation increases with number of dies (with hotspot heat fluxes up to 250W/cm2) generating high chip temperatures. In this context, inter-tier integrated microchannel cooling is a promising and scalable solution for high heat flux removal. A robust design of a 3D IC and its subsequent thermal management depend heavily upon accurate modeling of the effects of liquid cooling on the thermal behavior of the IC during the early stages of design. In this paper we present 3D-ICE, a compact transient thermal model (CTTM) for the thermal simulation of 3D ICs with multiple inter-tier microchannel liquid cooling. The proposed model is compatible with existing thermal CAD tools for ICs, and offers significant speed-up (up to 975x) over a typical commercial computational fluid dynamics simulation tool while preserving accuracy (i.e., maximum temperature error of 3.4%). In addition, a thermal simulator has been built based on 3D-ICE, which is capable of running in parallel on multicore architectures, offering further savings in simulation time and demonstrating efficient parallelization of the proposed approach.

3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

Abstract: Liquid-cooling using microchannel heat sinks etched on silicon dies is seen as a promising solution to the rising heat fluxes in two-dimensional and stacked three-dimensional integrated circuits. Development of such devices requires accurate and fast thermal simulators suitable for early-stage design. To this end, we present 3D-ICE, a compact transient thermal model (CTTM), for liquid-cooled ICs. 3D-ICE was first advanced incorporating the 4-resistor model-based CTTM (4RM-based CTTM). Later, it was enhanced to speed up simulations and to include complex heat sink geometries such as pin fins using the new 2 resistor model (2RM-based CTTM). In this paper, we extend the 3D-ICE model to include liquid-cooled ICs with multi-port cavities, i.e., cavities with more than one inlet and one outlet ports, and non-straight microchannels. Simulation studies using a realistic 3D multiprocessor system-on-chip (MPSoC) with a 4-port microchannel cavity highlight the impact of using 4-port cavity on temperature and also demonstrate the superior performance of 2RM-based CTTM compared to 4RM-based CTTM. We also present an extensive review of existing literature and the derivation of the 3D-ICE model, creating a comprehensive study of liquid-cooled ICs and their thermal simulation from the perspective of computer systems design. Finally, the accuracy of 3D-ICE has been evaluated against measurements from a real liquid-cooled 3D-IC, which is the first such validation of a simulator of this genre. Results show strong agreement (average error ${\bf \lt 10\%}$ ), demonstrating that 3D-ICE is an effective tool for early-stage thermal-aware design of liquid-cooled 2D-/3D-ICs.

Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries

Abstract: The advent of 3D stacked ICs with accumulating heat fluxes stresses thermal reliability and is responsible for temperature driven performance deterioration of the electronic systems Hot spots with power densities typically rising up to 250 W/cm2 are not acceptable, with the result of limited performance improvement in next generation highperformance microprocessor stacks. Unfortunately traditional back-side cooling only scales with the chip stack footprint, but not with the number of tiers. Direct heat removal from the IC dies via inter-tier liquid cooling is a promising solution to address this problem. In this regard, a thermal-aware design of a 3D IC with liquid cooling for optimal electronic performance and reliability requires fast modeling and simulation of the liquid cooling during the early stages of the design. In this paper, we propose a novel compact transient thermal modeling (CTTM) scheme for liquid cooling in 3D ICs via microchannels and enhanced heat transfer cavity geometries such as pin-fin structures. The model is compatible with the existing thermal-CAD tools for ICs and offers significant speed-up over commercial computational fluid dynamics simulators (13478x for pin-fin geometry with 1.1% error in temperature). In addition, the model is highly flexible and it provides a generic framework in which heat transfer coefficient data from numerical simulations or existing correlations can be incorporated depending upon the speed/accuracy needs of the designer. We have also studied the effects of using different techniques for the estimation of heat transfer coefficients on the accuracy of the model. This study highlights the need to consider developing flow conditions to accurately model the temperature field in the chip stack. The use of correlation data from fully developed flows only results in temperature error as high as 9 K (about 41%) near the inlet.

EigenMaps: algorithms for optimal thermal maps extraction and sensor placement on multicore processors

Abstract: Chip designers place on-chip sensors to measure local temperatures, thus preventing thermal runaway situations in multicore processing architectures. However, thermal characterization is directly dependent on the number of placed sensors, which should be minimized, while guaranteeing full detection of all hot-spots and worst case temperature gradient. In this paper, we present EigenMaps: a new set of algorithms to recover precisely the overall thermal map from a minimal number of sensors and a near-optimal sensor allocation algorithm. The proposed methods are stable with respect to possible temperature sensor calibration inaccuracies, and achieve significant improvements compared to the state-of-the-art. In particular, we estimate an entire thermal map for an industrial 8-core industrial design within 1°C of accuracy with just four sensors. Moreover, when the measurements are corrupted by noise (SNR of 15 dB), we can achieve the same precision only with 16 sensors.

Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs

Abstract: Heat removal is one of the major challenges faced in developing the new generation of high density integrated circuits. Future design technologies strongly depend on the availability of efficient means for thermal modeling and analysis. These thermal models must be also accurate and provide the most efficient level of abstraction enabling fast execution. We propose an innovative thermal simulation method based on Neural Networks that is able to solve the scalability problem of transient heat flow simulation in large 2D/3D multi-processor ICs by exploiting the computational power of massively parallel graphics processing units (GPUs).

Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory

Abstract: This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.

Near-Optimal Sensor Placement for Linear Inverse Problems

Abstract: A classic problem is the estimation of a set of parameters from measurements collected by only a few sensors. The number of sensors is often limited by physical or economical constraints and their placement is of fundamental importance to obtain accurate estimates. Unfortunately, the selection of the optimal sensor locations is intrinsically combinatorial and the available approximation algorithms are not guaranteed to generate good solutions in all cases of interest. We propose FrameSense, a greedy algorithm for the selection of optimal sensor locations. The core cost function of the algorithm is the frame potential, a scalar property of matrices that measures the orthogonality of its rows. Notably, FrameSense is the first algorithm that is near-optimal in terms of mean square error, meaning that its solution is always guaranteed to be close to the optimal one. Moreover, we show with an extensive set of numerical experiments that FrameSense achieves state-of-the-art performance while having the lowest computational cost, when compared to other greedy methods.

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

Abstract: In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50‐100W/cm 2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500W/cm 2 , significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200lm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops. [DOI: 10.1115/1.4027175]

Carbon Nanotube Robust Digital VLSI

Abstract: Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.