This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

We present in this paper a low-power bioamplifier suitable for massive integration in dense multichannel recording devices. This bioamplifier achieves reduced-size compared to previous designs by means of active low-frequency suppression. An active integrator located in the feedback path of a low-noise amplifier is employed for placing a highpass cutoff frequency within the transfer function. A very long integrating time constant is achieved using a small integrated capacitor and a MOS-bipolar equivalent resistor. This configuration rejects unwanted low-frequency contents without the need for input RC networks or large feedback capacitors. Therefore, the bioamplifier high-input impedance and small size are preserved. The bioamplifier, implemented in a 0.18-mum CMOS process, has been designed for neural recording of action potentials, and optimised through a transconductance-ef-ficiency design methodology for micropower operation. Measured performance and results obtained from in vivo recordings are presented. The integrated bioamplifier provides a midband gain of 50 dB, and achieves an input-referred noise of 5.6 muVrms. It occupies less than 0.050 mm2 of chip area and dissipates 8.6 muW.

A Low-Power Integrated Bioamplifier With Active Low-Frequency Suppression

A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data

The study of brain-computer interfaces (BCIs) has undergone 30 years of intense development and has grown into a rich and diverse field. BCIs are technologies that enable direct communication between the human brain and external devices. Conventionally, wet electrodes have been employed to obtain unprecedented sensitivity to high-temporal-resolution brain activity; recently, the growing availability of various sensors that can be used to detect high-quality brain signals in a wide range of clinical and everyday environments is being exploited. This development of biosensing neurotechnologies and the desire to implement them in real-world applications have led to the opportunity to develop augmented BCIs (ABCIs) in the upcoming decades. An ABCI is similar to a BCI in that it relies on biosensors that record signals from the brain in everyday environments; the signals are then processed in real time to monitor the behavior of the human. To use an ABCI as a mobile brain imaging technique for everyday, real-life applications, the sensors and the corresponding device must be lightweight and the equipment response time must be short. This study presents an overview of the wide range of biosensor approaches currently being applied to ABCIs, from their use in the laboratory to their application in clinical and everyday use. The basic principles of each technique are described along with examples of current applications of cutting-edge neuroscience research. In summary, we show that ABCI techniques continue to grow and evolve, incorporating new technologies and advances to address ever more complex and important neuroscience issues, with advancements that are envisioned to lead to a wide range of real-life applications.

https://ir.nctu.edu.tw:443/bitstream/11536/20522/1/000309838000041.pdf

Biosensor Technologies for Augmented Brain–Computer Interfaces in the Next Decades

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

/pdf/a-100-channel-1-mw-implantable-neural-recording-ic-2lulelpifv.pdf

A 100-Channel 1-mW Implantable Neural Recording IC

In this paper, series-parallel (SP) current-division will be employed for the design of very low transconductance OTAs. From the theory and measurements, it will be shown that SP mirrors allow the division of currents with division factors of thousands, without reducing matching or noise performance. SP mirrors will be applied to the design of OTAs ranging from 33 pS to a few nS, with up to 1 V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3-s time-constant integrator will also be presented. Several design concerns will be studied: linearity, offset, noise, and leakages, as well as layout techniques. A final comparative analysis concludes that SP association of transistors allows the design of very efficient transconductors, for demanding applications in the field of implantable electronics, among others

Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors

Simple, physics-based MOSFET noise models, valid over the linear, saturation, and subthreshold operation regions are presented. The consistency of the models representing series-parallel associations of transistors is verified. Simple formulas for hand analysis using the inversion level concept are developed. The proportionality between the flicker noise corner frequency and the transistor transition frequency is proved and experimentally verified under wide bias conditions. Application of the noise models to a low-noise design is shown.

Consistent noise models for analysis and design of CMOS circuits

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.

/pdf/a-compact-model-of-mosfet-mismatch-for-circuit-design-2zuggaaxlz.pdf

A compact model of MOSFET mismatch for circuit design

Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.

A compact model for flicker noise in MOS transistors for analog circuit design

A simple design procedure for very small transconductors with extended linear range, using series-parallel division of current, is presented. It is based on a previously reported one-equation all-region transistor model. Using this technique, a 33 pico-A/V transconductor equivalent to a 30 GΩ resistor is demonstrated.

/pdf/pico-a-v-range-cmos-transconductors-using-series-parallel-gsbg27amcd.pdf

Alfredo Arnaud

Papers

Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors

Consistent noise models for analysis and design of CMOS circuits

A compact model of MOSFET mismatch for circuit design

A compact model for flicker noise in MOS transistors for analog circuit design

Pico-A/V range CMOS transconductors using series-parallel current division