Ali AbdelKader

Bio: Ali AbdelKader is an academic researcher from American University in Cairo. The author has contributed to research in topics: Triple modular redundancy & Fault tolerance. The author has an hindex of 2, co-authored 3 publications receiving 21 citations.

FPGA-based reliable TMR controller design for S2A architectures

Abstract: Fault-tolerance is becoming an essential feature in the design of Networked Control Systems (NCSs). Furthermore, Sensor-to-Actuator (S2A) architectures have shown some advantages over conventional In-Loop architectures. This paper focuses on fault-tolerant controllers in the context of S2A systems. It proposes the use of Triple Modular Redundancy at the controller level. The fault-tolerant controller will be hosted in an FPGA that has a spare location. The voter in this TMR scheme is fault-secure to guarantee that the controllers never produce an undetected incorrect control action. Finally, system reliability is calculated using Markov models to quantitatively show, via case studies, the advantage of the proposed technique in terms of extended lifetime.

Integration of Multiple Fault-Tolerant techniques for FPGA-based NCS Nodes

Abstract: Fault-Tolerance is quickly becoming a very important issue in the design of industrial automation systems. This paper addresses this issue in the context of temporary failures occurring in harsh industrial environments. The Fault-Tolerant design of sensors and controllers is investigated for both the In-Loop and Sensor-to-Actuator architectures. Processing is implemented on FPGAs whenever possible. Triple Modular Redundancy (TMR) is used to implement sensors for fast varying applications while Temporal Redundancy (TR) is used for sensors for slow varying applications in order to reduce cost without affecting system reliability. Dynamic Partial Reconfiguration (DPR) is used for fault recovery. Reliability models are developed for all Fault-Tolerant blocks to help system designers with the choice of the Fault-Tolerant techniques to be implemented. Two case studies are carried out with different numbers of fast and slow sensors. System reliabilities are calculated for both conventional and hybrid NCS systems. Results show that the proposed technique results in a cost-effective system at the expense of a very slight decrease in reliability.

An Evaluation of RGB and LiDAR Fusion for Semantic Segmentation.

Abstract: LiDARs and cameras are the two main sensors that are planned to be included in many announced autonomous vehicles prototypes. Each of the two provides a unique form of data from a different perspective to the surrounding environment. In this paper, we explore and attempt to answer the question: is there an added benefit by fusing those two forms of data for the purpose of semantic segmentation within the context of autonomous driving? We also attempt to show at which level does said fusion prove to be the most useful. We evaluated our algorithms on the publicly available SemanticKITTI dataset. All fusion models show improvements over the base model, with the mid-level fusion showing the highest improvement of 2.7% in terms of mean Intersection over Union (mIoU) metric.

Highly reliable controller implementation using a network-based fully reconfigurable FPGA for industrial applications

Abstract: Fault-Tolerance is currently a very important feature in industrial automation. This paper focuses on Fault-Tolerant FPGA-based controllers for Sensor-to-Actuator Networked Control Systems. A design is proposed that takes advantage of the Dynamic Partial Reconfiguration property inherent in some FPGAs. The controller is assumed to consist of a small processor, memory and associated hardware. Several Fault-Tolerance techniques are applied to this generic system and single points of failure are avoided even in the error detection and recovery mechanisms. The fault model considered is single and/or some multiple event upsets. A case study is presented to quantify the increase in reliability of the presented system. Furthermore, the proposed architecture can support FPGA full configuration as well as partial reconfiguration over TCP/IP networks through on-chip configuration network interface with minimal off-chip components.

Fault secure FPGA-based TMR voter

Abstract: Nowadays, FPGAs are used in many safety-critical applications. They are mainly subjected to Single Event Upsets (SEUs) that can flip the state of a memory cell, thereby forcing the circuit to produce an erroneous output. Fault-tolerant techniques are used to mitigate these errors. Triple Modular Redundancy (TMR) is one of the most commonly used fault-tolerant techniques in FPGAs. However, the voter is a single point of failure. This paper proposes a fault secure TMR voter design. This voter is analyzed according to its FPGA implementation. SEUs, Single Event Transients (SETs) as well as single stuck-at-0(1) faults are considered. In the presence of these faults, this voter will always produce the correct output or will give an indication of the presence of an error. Alternating Logic is utilized in the design to help with error detection while Dynamic Partial Reconfiguration (DPR) is used for error recovery.

Integration of Multiple Fault-Tolerant techniques for FPGA-based NCS Nodes

Abstract: Fault-Tolerance is quickly becoming a very important issue in the design of industrial automation systems. This paper addresses this issue in the context of temporary failures occurring in harsh industrial environments. The Fault-Tolerant design of sensors and controllers is investigated for both the In-Loop and Sensor-to-Actuator architectures. Processing is implemented on FPGAs whenever possible. Triple Modular Redundancy (TMR) is used to implement sensors for fast varying applications while Temporal Redundancy (TR) is used for sensors for slow varying applications in order to reduce cost without affecting system reliability. Dynamic Partial Reconfiguration (DPR) is used for fault recovery. Reliability models are developed for all Fault-Tolerant blocks to help system designers with the choice of the Fault-Tolerant techniques to be implemented. Two case studies are carried out with different numbers of fast and slow sensors. System reliabilities are calculated for both conventional and hybrid NCS systems. Results show that the proposed technique results in a cost-effective system at the expense of a very slight decrease in reliability.

FPGA-based reliable video sensor in NC

Abstract: Recently, FPGA-based NCS applications have been widely used. Industrial environments have a lot of electromagnetic interference which may induce transient and permanent faults. As a result, Fault-Tolerant FPGA based NCS applications are required. In this paper, an NCS model composed of a combination of S2A architecture and In-Loop architecture connected to each other through Ethernet switch, is described. The S2A part of the model is an FPGA-based video sensor network which requires protection against transient faults. Several Fault-Tolerant techniques are mentioned in the literature for protection. Two Fault-Tolerant techniques are under study which are Hot Standby and Sift-Out. The fault model used is Single Event Upsets (SEUs). Dynamic Partial Recovery is used. Markov Models are used for reliability calculations. Results show that even though the Sift-Out technique is more reliable than Hot Standby, there may be situations where the difference in reliability cannot justify the extra cost.

Error Detection and Recovery in FPGA-based Pipelined Architectures

Abstract: In safety-critical applications, it is very important for the system to be very reliable. This paper focuses on such applications when implemented with pipelined architectures on SRAM-based FPGAs. The fault model consists of Hard Faults and Single Event Upsets (SEUs). Three different architectures are proposed to add fault detection and/or recovery in order to increase system reliability. It is shown that these improvements are made at a small cost in terms of area, power consumption and performance. An Altera Cyclone IV E FPGA is used to explain the design and the architectures’ behaviors while Markov models are used to calculate reliability increase.